本文選題：DSP內(nèi)核 + 代碼優(yōu)化��； 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：YHFT-DX DSP內(nèi)核的性能是YHFT-DX高性能數(shù)字信號處理器設(shè)計性能的關(guān)鍵，它采用65nm工藝，要求頻率從原有頻率600MHz提升到目標(biāo)頻率800MHz。論文以YHFT-DXDSP內(nèi)核的數(shù)據(jù)通路和一級Cache的性能優(yōu)化為背景，對RTL級代碼優(yōu)化方法，電路設(shè)計優(yōu)化技術(shù)，以及全定制與半定制相結(jié)合的設(shè)計方法進(jìn)行了研究，，主要完成了以下工作： 1．對DSP內(nèi)核的功能部件和一級Cache做RTL級代碼優(yōu)化，重點(diǎn)優(yōu)化時序緊張的訪存部件和乘法部件，通常采用的有效方法包括：減少端口復(fù)用，邏輯移棧、邏輯復(fù)制、算法并行化等。通過RTL級代碼優(yōu)化，DSP內(nèi)核在1ns時鐘周期內(nèi)時序收斂。 2．利用全定制與半定制相結(jié)合的方法實(shí)現(xiàn)DSP內(nèi)核關(guān)鍵路徑上的加法器和乘法器。訪存部件中的32位加法器采用基于標(biāo)準(zhǔn)單元的手工半定制實(shí)現(xiàn)，版圖后模擬表明，該加法器延時和全定制加法器的延時基本一致，但設(shè)計周期大大縮短。16位SIMD乘法器的關(guān)鍵路徑采用全定制實(shí)現(xiàn)，非關(guān)鍵路徑采用半定制實(shí)現(xiàn)，版圖后模擬結(jié)果表明該乘法器延時比半定制設(shè)計減少了24%。合理利用這兩種方法，可以在提升設(shè)計性能的同時減小設(shè)計周期。 3．為了驗證YHFT-DX DSP內(nèi)核的優(yōu)化工作是否有效，設(shè)計了一款內(nèi)核測試芯片，并對流片之后的測試芯片做板級測試，測試結(jié)果顯示YHFT-DX DSP內(nèi)核能夠在1.0v典型CMOS工藝條件下達(dá)到900MHz，且功能正確，達(dá)到了目標(biāo)頻率。綜上所述，DSP內(nèi)核的優(yōu)化方法是切實(shí)可行和有效的。
[Abstract]:The performance of YHFT-DX DSP kernel is the key to the design performance of YHFT-DX high performance digital signal processor. It adopts 65nm technology and requires the frequency to be increased from 600MHz to 800MHz. Based on the data path of the YHFT-DX DSP kernel and the performance optimization of the first level cache, this paper studies the RTL-level code optimization method, circuit design optimization technology, and the design method of the combination of full-customization and semi-customization. The main works are as follows: 1. RTL-level code optimization of DSP kernel and one level cache is done, and the memory access and multiplication components with tight timing are optimized. The effective methods usually adopted include reducing port reuse. Logic shift stack, logical copy, algorithm parallelization, etc. The RTL-level code is used to optimize the timing convergence of the 1ns kernel during the clock cycle. 2. The adder and multiplier on the critical path of the 1ns kernel are realized by the combination of full customization and semi-customization. The 32-bit adder in memory access unit is realized by manual semi-customization based on standard cell. The simulation after layout shows that the delay of the adder is basically the same as that of the fully customized adder. However, the design cycle is greatly shortened. The critical path of the .16-bit SIMD multiplier is realized by full customization, while the non-critical path is implemented by semi-customization. The simulation results after layout show that the delay of the multiplier is 24% less than that of semi-custom design. Reasonable use of these two methods can improve the design performance while reducing the design cycle. 3. In order to verify the effectiveness of the optimization of the YHFT-DX DSP kernel, a kernel test chip is designed. The experimental results show that the YHFT-DX DSP core can reach 900MHz in 1.0v typical CMOS process, and the function is correct and the target frequency is achieved. To sum up, the optimization method of DSP kernel is feasible and effective.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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