本文選題：同時(shí)多線程處理器 + 取指控制機(jī)制　； 參考：《哈爾濱工程大學(xué)》2012年碩士論文

【摘要】：隨著計(jì)算機(jī)體系結(jié)構(gòu)的發(fā)展，為順應(yīng)人們對(duì)高性能處理器的迫切需求，同時(shí)多線程處理器應(yīng)運(yùn)而生，成為目前主流的微處理器結(jié)構(gòu)。針對(duì)同時(shí)多線程處理器的各項(xiàng)研究變得十分活躍，同時(shí)多線程處理器的取指控制機(jī)制作為高性能處理器領(lǐng)域的研究熱點(diǎn)備受關(guān)注。近年來，國(guó)內(nèi)外許多專家學(xué)者和科研機(jī)構(gòu)對(duì)其展開積極的研究和探索。但是，目前同時(shí)多線程處理器的取指控制技術(shù)仍存在取指帶寬利用不均衡、指令隊(duì)列沖突率高和分支預(yù)測(cè)性能低下等缺陷。因此，本文將針對(duì)同時(shí)多線程處理器的取指控制技術(shù)展開研究，以尋求高效合理的取指控制機(jī)制。 本文首先從取指策略和分支預(yù)測(cè)器兩個(gè)方面對(duì)取指控制機(jī)制進(jìn)行研究，并分別提出一種基于同時(shí)多線程的取指策略和分支預(yù)測(cè)器。與傳統(tǒng)的取指策略相比，本策略的技術(shù)優(yōu)勢(shì)：處理器的取指過程分為線程選擇、取指帶寬劃分和動(dòng)態(tài)資源分配三個(gè)階段，通過計(jì)算線程運(yùn)行所需的指令數(shù)，給予適量的取指帶寬，使得取指帶寬的利用更為均衡。同時(shí)，根據(jù)線程的優(yōu)先級(jí)動(dòng)態(tài)分配系統(tǒng)資源，提高了系統(tǒng)資源的利用率。在新型取指策略研究的基礎(chǔ)上，，設(shè)計(jì)與之相對(duì)應(yīng)的分支預(yù)測(cè)器，通過將線程的全局和局部歷史信息相結(jié)合作為分支預(yù)測(cè)信息位，有效地克服了傳統(tǒng)機(jī)制中分支預(yù)測(cè)信息混亂、不完整等現(xiàn)象的發(fā)生。同時(shí)，通過新增分支結(jié)果輸出表BRT記錄常見分支指令的預(yù)測(cè)結(jié)果，推進(jìn)了指令的分支預(yù)測(cè)執(zhí)行速度。通過綜合這兩項(xiàng)研究成果，提出一種基于同時(shí)多線程的取指控制機(jī)制，有效地提高了處理器的指令吞吐率和分支預(yù)測(cè)性能。 最后，通過設(shè)計(jì)合理的性能測(cè)試方案，對(duì)其進(jìn)行性能測(cè)試和結(jié)果分析。性能測(cè)試結(jié)果表明：新型的取指控制機(jī)制有效地克服了傳統(tǒng)機(jī)制中存在的取指策略不夠優(yōu)化、分支預(yù)測(cè)性能低下等缺點(diǎn)，極大地促進(jìn)處理器整體性能的提升，具有良好的應(yīng)用前景和研究?jī)r(jià)值。
[Abstract]:With the development of computer architecture, in order to meet the urgent needs of high performance processors, multithread processors emerge as the times require, and become the mainstream microprocessor architecture. The research on simultaneous multithreading processor has become very active, and the control mechanism of multi-threaded processor as the research hotspot in the field of high-performance processors. In recent years, many domestic and foreign experts and scholars and scientific research institutions to carry out active research and exploration. However, at present, there are still some shortcomings in the simultaneous multithread processor, such as unbalanced utilization of the wideband, high collision rate of instruction queue and low branch prediction performance. Therefore, this paper will focus on the simultaneous multithreaded processor to research the technology of finger extraction control, in order to find an efficient and reasonable control mechanism. In this paper, we first study the control mechanism of finger extraction from two aspects: the strategy of finger extraction and the branch predictor, and propose a new strategy and a branch predictor based on simultaneous multithreading respectively. Compared with the traditional strategy, the technology advantage of this strategy is as follows: the process of the processor is divided into three stages: thread selection, bandwidth partition and dynamic resource allocation, and the number of instructions needed for thread operation is calculated. Give the appropriate amount of finger-taking bandwidth, so that the use of finger-taking bandwidth more balanced. At the same time, the system resource is dynamically allocated according to the priority of thread, and the utilization rate of system resource is improved. A branch predictor is designed based on the research of the new strategy of finger extraction. By combining the global and local historical information of thread as the bit of branch prediction information, the confusion of branch prediction information in the traditional mechanism is effectively overcome. The occurrence of incomplete phenomena. At the same time, the new branch result output table (BRT) records the prediction results of common branch instructions, which promotes the execution speed of branch prediction. By synthesizing these two research results, a new control mechanism based on simultaneous multithreading is proposed, which can effectively improve the instruction throughput and branch prediction performance of the processor. Finally, through the design of a reasonable performance test scheme, the performance test and results analysis. The performance test results show that the new control mechanism overcomes the shortcomings of the traditional mechanism, such as poor performance of branch prediction and poor performance of branch prediction, which can greatly improve the overall performance of the processor. It has good application prospect and research value.
【學(xué)位授予單位】：哈爾濱工程大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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