本文選題：嵌入式存儲器 + 可測性設(shè)計　； 參考：《西安電子科技大學(xué)》2013年碩士論文

【摘要】：隨著半導(dǎo)體集成技術(shù)的發(fā)展及SoC的廣泛應(yīng)用，芯片結(jié)構(gòu)中嵌入式存儲器所占比重不斷加大。而存儲器本身的高密度結(jié)構(gòu)和復(fù)雜的制造工藝增大了其出現(xiàn)物理缺陷的可能性，使其成為制約芯片成品率的關(guān)鍵因素。因而，研究高效的嵌入式存儲器可測性設(shè)計方法以及失效存儲器的修復(fù)技術(shù)變得十分重要，并具有廣闊的應(yīng)用前景。 論文闡述了嵌入式存儲器測試與修復(fù)技術(shù)的國內(nèi)外研究狀況，針對傳統(tǒng)的測試和修復(fù)技術(shù)效率較低的問題，，通過分析芯片的可測性設(shè)計原理，設(shè)計了基于March16N測試算法的16k×16位SRAM內(nèi)建自測試電路及其在芯片中的頂層連接電路；采用冗余寄存器代替存儲器故障單元的方法，設(shè)計了基于E-fuse可編程熔絲結(jié)構(gòu)的存儲器片上修復(fù)系統(tǒng)。使用Modelsim工具對內(nèi)建自測試電路進行了模擬仿真，驗證了該電路功能的正確性。對修復(fù)電路進行了模擬仿真和后端設(shè)計，結(jié)果表明該系統(tǒng)可實現(xiàn)存儲器故障修復(fù)，且增加的電路面積小于原存儲器面積的10%，達到了預(yù)期功能。在以上研究基礎(chǔ)上，針對芯片中需要修復(fù)的存儲器較多的情況，對片上修復(fù)系統(tǒng)進行了優(yōu)化，進一步減小修復(fù)電路占用的面積。為嵌入式存儲器測試及修復(fù)技術(shù)的發(fā)展提供了技術(shù)支撐。
[Abstract]:With the development of semiconductor integration technology and the wide application of SoC, the proportion of embedded memory in chip structure is increasing. The high density structure of the memory and the complex manufacturing process increase the possibility of physical defects and make it the key factor to restrict the yield of the chip. Therefore, it is very important to study the efficient design method of the testability of embedded memory and the repair technology of the invalid memory, and it has a broad application prospect. This paper describes the research status of embedded memory test and repair technology at home and abroad. Aiming at the low efficiency of traditional test and repair technology, this paper analyzes the design principle of chip testability. A 16 k 脳 16 bit SRAM built-in self-test circuit based on March16N test algorithm and its top-level connection circuit in the chip are designed, and the method of using redundant registers instead of memory fault cells is designed. A memory on-chip repair system based on E-fuse programmable fuse structure is designed. Simulation of built-in self-test circuit with Modelsim is carried out, and the correctness of the circuit is verified. The simulation and back-end design of the repair circuit are carried out. The results show that the system can realize the memory fault repair, and the increased circuit area is less than 10% of the original memory area, which achieves the expected function. On the basis of the above research, the on-chip repair system is optimized to reduce the area occupied by the repair circuit in view of the more memory needed to be repaired in the chip. It provides technical support for the development of embedded memory test and repair technology.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333;TN47

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