本文選題：NAND閃存 + 多層單元(MLC)存儲(chǔ)技術(shù)　； 參考：《廣東工業(yè)大學(xué)》2017年碩士論文

【摘要】：隨著電子產(chǎn)品的普及,人們每天在互聯(lián)網(wǎng)與移動(dòng)互聯(lián)網(wǎng)上產(chǎn)生大量的數(shù)據(jù),數(shù)據(jù)變得越來(lái)越重要,未來(lái)將進(jìn)入一個(gè)數(shù)據(jù)的時(shí)代。對(duì)于這些龐大的數(shù)據(jù),需要設(shè)備來(lái)進(jìn)行存儲(chǔ)。NAND閃存作為一種非易失存儲(chǔ)器件已在電子產(chǎn)品、數(shù)據(jù)存儲(chǔ)系統(tǒng)中得到了廣泛的使用。為了滿足大容量數(shù)據(jù)存儲(chǔ)的需求,多層單元(MLC)存儲(chǔ)技術(shù)的出現(xiàn)突破了原本單層單元(SLC)存儲(chǔ)技術(shù)的局限。MLC存儲(chǔ)技術(shù)通過(guò)在單個(gè)閃存單元中存儲(chǔ)多個(gè)比特信息,提高了NAND閃存的存儲(chǔ)密度。然而,制作工藝不斷縮小NAND閃存的芯片尺寸,導(dǎo)致了相鄰閃存單元間的干擾(CCI)變得越來(lái)越嚴(yán)重,成為了目前影響NAND閃存存儲(chǔ)可靠性的主要因素。除此之外,在存儲(chǔ)過(guò)程中還存在著其他噪聲以及NAND閃存使用壽命的影響,這些干擾都會(huì)使得數(shù)據(jù)在存儲(chǔ)及讀取過(guò)程中出現(xiàn)錯(cuò)誤。如何提高高密度NAND閃存的存儲(chǔ)可靠性,已經(jīng)成為了目前存儲(chǔ)研究的熱點(diǎn)。常用的糾錯(cuò)方法有通過(guò)采用合適的糾錯(cuò)碼型和有效的譯碼算法,在信息寫入到NAND閃存塊之前進(jìn)行編碼操作,在信息讀取之后進(jìn)行譯碼操作,最后還原出原始信息,從而提高存儲(chǔ)可靠性。另外,信號(hào)處理方法也是另外一個(gè)提高存儲(chǔ)可靠性的新途徑,例如對(duì)NAND閃存閾值電壓信號(hào)的預(yù)處理技術(shù)和后補(bǔ)償處理技術(shù)。本文主要對(duì)高密度NAND閃存信道進(jìn)行了深入的分析與仿真,并在此基礎(chǔ)上開展了低復(fù)雜度糾錯(cuò)技術(shù)的研究。具體工作如下:(1)結(jié)合高密度NAND閃存的結(jié)構(gòu)、擦除編程原理及相鄰閃存單元間干擾的特性,建立一個(gè)高密度NAND閃存信道仿真模型。在此信道模型的基礎(chǔ)上,可以方便地進(jìn)行高密度NAND閃存的糾錯(cuò)技術(shù)研究。通過(guò)對(duì)信道模型中的信道參數(shù)及干擾因子進(jìn)行設(shè)置,可以觀察糾錯(cuò)方法在高密度NAND閃存的性能表現(xiàn),從而設(shè)計(jì)出有效的糾錯(cuò)方法。(2)從差錯(cuò)控制編碼方向上,采用了在目前流行的、具有優(yōu)異糾錯(cuò)性能的低密度奇偶校驗(yàn)(LDPC)碼作為高密度NAND閃存的糾錯(cuò)碼型,同時(shí)結(jié)合高密度閃存信道的特性設(shè)計(jì)了一種改進(jìn)型軟可靠性迭代大數(shù)邏輯譯碼(modified SRBI-MLGD,MSRBI-MLGD)算法,從而提高了信息存儲(chǔ)的可靠性。該算法在保持較好糾錯(cuò)性能的同時(shí),又降低了譯碼的復(fù)雜度。(3)從信號(hào)處理方向上,提出了一種低檢測(cè)延時(shí)的后補(bǔ)償(LL-Post-comp)信號(hào)處理方法。NAND閃存單元的比特信息實(shí)際是通過(guò)閃存單元的閾值電壓表示的。當(dāng)NAND閃存發(fā)生干擾時(shí),閃存單元的閾值電壓就會(huì)發(fā)生變化從而導(dǎo)致比特信息出錯(cuò)。該后補(bǔ)償信號(hào)處理方法可以對(duì)被干擾閃存單元閾值電壓進(jìn)行補(bǔ)償,從而提高存儲(chǔ)的可靠性。同時(shí)在檢測(cè)閃存單元的閾值電壓上,只產(chǎn)生較低延時(shí)的開銷。
[Abstract]:With the popularity of electronic products, people produce a large number of data on the Internet and mobile Internet every day, data become more and more important, the future will enter a data era. For these huge data, it is necessary to store .NAND flash memory. As a non-volatile memory device, it has been widely used in electronic products and data storage systems. In order to meet the demand of large capacity data storage, the emergence of multilayer cell (MLC) memory technology breaks through the limitation of the original single-layer unit (SLC) storage technology. MLC memory technology stores multiple bits of information in a single flash memory unit. The storage density of NAND flash memory is improved. However, the fabrication process has reduced the chip size of NAND flash memory, resulting in more and more interference between adjacent flash memory units, which has become the main factor affecting the reliability of NAND flash memory. In addition, there are other noises in the stored procedure and the influence of the NAND flash memory lifetime, which will cause errors in the data storage and reading process. How to improve the storage reliability of high density NAND flash memory has become a hot research topic. The commonly used error correction methods include coding operation before the information is written to the NAND flash block, decoding operation after reading the information, and restoring the original information by adopting the appropriate error correction code type and effective decoding algorithm. Thus, the storage reliability is improved. In addition, signal processing is another new way to improve storage reliability, such as pre-processing of NAND flash threshold voltage signal and post-compensation processing. In this paper, the high density NAND flash channel is deeply analyzed and simulated, and the low complexity error correction technology is studied. The main work is as follows: 1) combined with the structure of high density NAND flash memory, erasure programming principle and the characteristics of interference between adjacent flash memory units, a channel simulation model of high density NAND flash memory is established. On the basis of this channel model, the error correction technology of high density NAND flash memory can be conveniently studied. By setting the channel parameters and interference factors in the channel model, the performance of error correction method in high density NAND flash memory can be observed, and an effective error correction method. The low density parity check (LDPC) codes, which are popular at present and have excellent error-correcting performance, are used as error correction codes for high-density NAND flash memory. At the same time, a modified SRBI-MLGDU MSRBI-MLGDX algorithm is designed to improve the reliability of information storage by combining the characteristics of high-density flash channel. The algorithm not only maintains better error-correcting performance, but also reduces the complexity of decoding. A low detection delay post-compensated LL-Post-compp signal processing method is proposed. The bit information of NAND flash memory unit is actually expressed by the threshold voltage of the flash memory unit. When the NAND flash is interfered, the threshold voltage of the flash memory unit changes, resulting in bit error. The post-compensation signal processing method can compensate the threshold voltage of the disturbed flash memory unit, so as to improve the reliability of the memory. At the same time, the threshold voltage of the flash memory unit is detected only with lower delay overhead.
【學(xué)位授予單位】：廣東工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP333;TN911.22

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本文編號(hào)：1975813