本文選題：加固設(shè)計(jì) + 流水線��； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：隨著計(jì)算機(jī)技術(shù)和微電子技術(shù)的不斷發(fā)展，航天級(jí)處理器在星載和宇航系統(tǒng)中得到了不斷的應(yīng)用。我校自主設(shè)計(jì)和實(shí)現(xiàn)的RAD_X處理器就是這樣一款航天級(jí)同構(gòu)四核芯片。設(shè)計(jì)航天級(jí)芯片時(shí)必須在電路設(shè)計(jì)時(shí)就進(jìn)行特別考慮，以避免空間輻照對(duì)電路工作的不利影響。本論文針對(duì)RAD_X處理器多個(gè)核心部件的抗輻照需求，設(shè)計(jì)和實(shí)現(xiàn)了多種加固電路。本課題基于0.13um CMOS工藝，采用半定制的設(shè)計(jì)流程，對(duì)該處理器核心部件進(jìn)行了全面的加固邏輯設(shè)計(jì)和驗(yàn)證。論文研究的主要內(nèi)容和工作成果包括以下幾個(gè)方面： 初步研究與分析了空間輻射的復(fù)雜環(huán)境，并總結(jié)了影響芯片可靠性的幾種輻射效應(yīng)。在體系架構(gòu)基礎(chǔ)上針對(duì)SEU的影響，提出了RAD_X體系結(jié)構(gòu)級(jí)的加固設(shè)計(jì)策略。 針對(duì)內(nèi)核整數(shù)部件流水線棧寄存器和寄存器文件的結(jié)構(gòu)特點(diǎn)和抗輻照要求，提出了流水線棧寄存器的三模冗余加固方案以及寄存器文件的擴(kuò)展?jié)h明碼加固方案，并進(jìn)行了邏輯實(shí)現(xiàn)和可靠性驗(yàn)證。 針對(duì)Cache系統(tǒng)的總體結(jié)構(gòu)特點(diǎn)和抗輻照要求，提出了對(duì)其進(jìn)行分組奇偶校驗(yàn)碼加固設(shè)計(jì)的方案并通過數(shù)據(jù)重載更新其出錯(cuò)數(shù)據(jù)，并進(jìn)行了邏輯實(shí)現(xiàn)和可靠性驗(yàn)證。 針對(duì)主存控制器的總體結(jié)構(gòu)特點(diǎn)和抗輻照要求，提出了對(duì)其進(jìn)行BCH校驗(yàn)碼加固設(shè)計(jì)的方案，并進(jìn)行了邏輯實(shí)現(xiàn)和可靠性驗(yàn)證。 經(jīng)模擬仿真以及FPGA驗(yàn)證，本論文所做的所有加固設(shè)計(jì)功能正確。芯片的工作頻率可以達(dá)到100MHz。理論分析表明，，芯片的故障率從0.4596錯(cuò)誤/設(shè)備一天降低到2.161195e-8錯(cuò)誤/設(shè)備-天。這些指標(biāo)都已經(jīng)完全達(dá)到了預(yù)定的性能。
[Abstract]:With the development of computer technology and microelectronics technology, spaceflight processors have been used in spaceborne and aerospace systems. Our own design and implementation of the RAD_X processor is such a spaceflight-level isomorphism four-core chip. In order to avoid the adverse effects of space irradiation on circuit operation, special consideration should be given to the design of spaceflight chips. In order to meet the radiation resistance requirement of several core components of RAD_X processor, a variety of reinforcement circuits are designed and implemented in this paper. Based on the 0.13um CMOS process, the core components of the processor are designed and verified by semi-custom design process. The main contents and work results of the thesis include the following aspects: The complex environment of space radiation is preliminarily studied and analyzed, and several radiation effects affecting the reliability of the chip are summarized. According to the influence of SEU, the reinforcement design strategy of RAD_X architecture level is put forward on the basis of architecture. According to the structural characteristics and irradiation-resistant requirements of pipeline stack registers and register files of kernel integers, this paper proposes a three-mode redundancy reinforcement scheme for pipeline stack registers and an extended hamming code reinforcement scheme for register files. Logic realization and reliability verification are also carried out. According to the overall structural characteristics and irradiation-resistant requirements of Cache system, a scheme of block parity check code reinforcement design is proposed, and the error data is updated by data overload, and the logic implementation and reliability verification are carried out. According to the overall structure characteristics and irradiation-resistant requirements of the main memory controller, the scheme of BCH check code reinforcement design is proposed, and the logic realization and reliability verification are carried out. Through simulation and FPGA verification, all the reinforcement design functions of this paper are correct. The working frequency of the chip can reach 100 MHz. Theoretical analysis shows that the failure rate of the chip is reduced from 0.4596 error / device per day to 2.161195e-8 error / device-day. These indicators have fully achieved the intended performance.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332;V446

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