本文選題：非對(duì)稱多核處理器 + 操作系統(tǒng)調(diào)度�。� 參考：《華南理工大學(xué)》2013年博士論文

【摘要】：隨著芯片集成規(guī)模極限的逼近以及能耗和成本等因素，多核處理器逐漸占據(jù)了市場(chǎng)。相對(duì)于對(duì)稱多核處理器，非對(duì)稱多核處理器在效能、芯片面積、適用范圍等方面有著巨大的優(yōu)勢(shì)，將成為未來(lái)的主流體系結(jié)構(gòu)�，F(xiàn)有調(diào)度算法從單核處理器發(fā)展而來(lái)，并為對(duì)稱多處理器做了相應(yīng)擴(kuò)展，不能利用非對(duì)稱多核處理器的特性和優(yōu)勢(shì)。本文致力于研究非對(duì)稱多核處理器的調(diào)度問(wèn)題，以提高系統(tǒng)的效能、性能和公平性。 具體來(lái)說(shuō)，本文從以下4個(gè)方面進(jìn)行了深入研究： (1)針對(duì)非對(duì)稱多核處理器上操作系統(tǒng)的單線程任務(wù)調(diào)度問(wèn)題，本文建模分析各種因素，提出了一種綜合性調(diào)度算法。該算法采用行為匹配、減少遷移和負(fù)載均衡的調(diào)度策略，包括兩個(gè)部分：1)集成負(fù)載表征，提出集成行為的概念，全面衡量任務(wù)的整體性和階段性行為；2)基于集成行為的調(diào)度算法，有效開(kāi)發(fā)非對(duì)稱多核處理器的特性，能夠保證各核心負(fù)載均衡，同時(shí)可以避免不必要的任務(wù)遷移。另外，該算法通過(guò)參數(shù)調(diào)整機(jī)制實(shí)現(xiàn)了算法的通用性。該算法是一種綜合處理任務(wù)的整體性和階段性行為，并具備通用性的調(diào)度算法。實(shí)驗(yàn)結(jié)果表明：該算法可通用于多種環(huán)境，且性能比其他同類算法提高6%~22%。 (2)針對(duì)非對(duì)稱多核處理器上操作系統(tǒng)的多線程任務(wù)調(diào)度問(wèn)題，本文建模分析各種因素，，提出了一個(gè)集成調(diào)度算法。該算法具有以下特性：1)全面考慮多線程任務(wù)同步特性、核心非對(duì)稱性以及核心負(fù)載；2)通過(guò)集成線程調(diào)度和動(dòng)態(tài)電壓頻率調(diào)整來(lái)提高效能；3)通過(guò)參數(shù)調(diào)整機(jī)制實(shí)現(xiàn)了算法的通用性。該算法是第一個(gè)在非對(duì)稱多核處理器上結(jié)合線程調(diào)度和動(dòng)態(tài)電壓頻率調(diào)整的調(diào)度算法。實(shí)驗(yàn)結(jié)果表明：該算法可適用于多種環(huán)境，且效能比其他同類算法高24%~50%。 (3)針對(duì)非對(duì)稱多核處理器上的虛擬處理器公平調(diào)度問(wèn)題，本文建模分析各種因素，提出了一個(gè)組合調(diào)度算法。該算法具有以下特性：1)全面考慮虛擬處理器同步特性、核心非對(duì)稱性以及核心負(fù)載；2)定義了效用因子、比例系數(shù)、比例資源的概念，結(jié)合虛擬處理器的同步特性和核心的非對(duì)稱性對(duì)資源和負(fù)載進(jìn)行全面度量；3)通過(guò)運(yùn)行隊(duì)列分解降低調(diào)度開(kāi)銷。實(shí)驗(yàn)結(jié)果表明：該算法實(shí)現(xiàn)了公平調(diào)度，并且性能比其他同類算法提高19%~48%。 (4)針對(duì)非對(duì)稱多核處理器上的虛擬處理器高效能調(diào)度問(wèn)題，本文提出一個(gè)并行度感知調(diào)度器，該調(diào)度器綜合利用了虛擬處理器調(diào)度和動(dòng)態(tài)電壓頻率調(diào)整。并行度感知調(diào)度器用一種非入侵的方法動(dòng)態(tài)監(jiān)測(cè)虛擬機(jī)的并行度，然后選擇并調(diào)度相關(guān)的虛擬處理器同時(shí)執(zhí)行。提出的推遲協(xié)同調(diào)度算法使多個(gè)并行的虛擬機(jī)可以同時(shí)進(jìn)行協(xié)同調(diào)度，而不會(huì)導(dǎo)致沖突。實(shí)際平臺(tái)上的實(shí)驗(yàn)表明，并行度感知調(diào)度器的性能和效能優(yōu)勢(shì)明顯，分別達(dá)到26%和65%。此外，并行度感知調(diào)度器的開(kāi)銷接近默認(rèn)調(diào)度器，低于其他非對(duì)稱多核處理器上的虛擬機(jī)調(diào)度器。
[Abstract]:With the approximation of chip integration scale limit, energy consumption and cost and other factors, multi core processors gradually occupy the market. Compared with symmetric multicore processors, asymmetric multicore processors have great advantages in efficiency, chip area, application scope and so on, and will become the mainstream architecture in the future. The existing scheduling algorithms are from single core processing. The device has developed and expanded for symmetric multiprocessors, and can not take advantage of the characteristics and advantages of asymmetric multicore processors. This paper is devoted to the research of scheduling problems of asymmetric multicore processors to improve system performance, performance and fairness.
Specifically, this paper makes an in-depth study from the following 4 aspects:
(1) aiming at the single thread task scheduling problem of the operating system on the asymmetric multi core processor, this paper presents a comprehensive scheduling algorithm based on the modeling and analysis of various factors. This algorithm uses behavior matching to reduce the migration and load balancing scheduling strategy, including two parts: 1) integration of load characterization, the concept of integrated behavior and a comprehensive balance. The overall and phased behavior of a task; 2) a scheduling algorithm based on integrated behavior, which can effectively develop the characteristics of asymmetric multicore processors, can guarantee the balance of all core loads and avoid unnecessary task migration. In addition, the algorithm realizes the generality of the algorithm through the parameter adjustment mechanism. This algorithm is a comprehensive treatment. The experimental results show that the algorithm can be used in many environments, and the performance of the algorithm is improved by 6%~22%. compared with other similar algorithms.
(2) aiming at the multi thread task scheduling problem of the operating system on the asymmetric multi core processor, this paper presents an integrated scheduling algorithm based on the modeling and analysis of various factors. This algorithm has the following characteristics: 1) taking into account the synchronization characteristics of multithreading tasks, core asymmetry and core load; 2) through integrated thread scheduling and dynamic voltage frequency integration. The algorithm is the first scheduling algorithm combined with thread scheduling and dynamic voltage frequency adjustment on an asymmetric multi core processor. The experimental results show that the algorithm can be applied to a variety of environments and the efficiency is 24%~50%. higher than the other similar algorithms, 24%~50%..
(3) aiming at the fair scheduling problem of virtual processors on asymmetric multicore processors, this paper presents a combination scheduling algorithm based on the modeling and analysis of various factors. This algorithm has the following characteristics: 1) taking into account the synchronization characteristics of the virtual processor, core asymmetry and core negative load; 2) defines the utility factor, the ratio coefficient, and the proportional resource. The concept, combining the synchronization characteristics of the virtual processor and the non symmetry of the core, makes a comprehensive measurement of the resources and the load; 3) reducing the scheduling overhead through the run queue decomposition. The experimental results show that the algorithm achieves fair scheduling and improves the performance of 19%~ 48%. compared with other similar algorithms.
(4) aiming at the efficient scheduling problem of virtual processors on asymmetric multi core processors, a parallel degree aware scheduler is proposed. The scheduler uses virtual processor scheduling and dynamic voltage frequency adjustment. The parallel degree aware scheduler dynamically monitors the parallelism of the virtual machine with a non intrusive method, and then selects and adjusts the degree. The proposed deferred collaborative scheduling algorithm enables multiple parallel virtual machines to perform collaborative scheduling at the same time without causing conflicts. Experiments on the actual platform show that the performance and effectiveness advantage of the parallel degree aware scheduler is obvious, up to 26% and 65%. respectively, and the parallel degree aware scheduler is open, respectively. The pin is close to the default scheduler, which is lower than the virtual machine scheduler on other asymmetric multi-core processors.
【學(xué)位授予單位】：華南理工大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332;TP301.6

【參考文獻(xiàn)】

相關(guān)期刊論文 前6條

1 鄧亞丹;景寧;熊偉;;多核處理器中基于Radix-Join的嵌套循環(huán)連接優(yōu)化[J];計(jì)算機(jī)研究與發(fā)展;2010年06期

2 蔣建春;汪同慶;;異構(gòu)多核處理器的任務(wù)調(diào)度算法[J];計(jì)算機(jī)工程與應(yīng)用;2009年33期

3 林闖;田源;姚敏;;綠色網(wǎng)絡(luò)和綠色評(píng)價(jià):節(jié)能機(jī)制、模型和評(píng)價(jià)[J];計(jì)算機(jī)學(xué)報(bào);2011年04期

4 彭蔓蔓;徐立超;王穎;;異構(gòu)多核處理器的任務(wù)分配及能耗的研究[J];計(jì)算機(jī)應(yīng)用研究;2010年05期

5 陳國(guó)良;孫廣中;徐云;龍柏;;并行計(jì)算的一體化研究現(xiàn)狀與發(fā)展趨勢(shì)[J];科學(xué)通報(bào);2009年08期

6 馮登國(guó);張敏;張妍;徐震;;云計(jì)算安全研究[J];軟件學(xué)報(bào);2011年01期

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