本文選題：網(wǎng)絡(luò)處理器 + 處理模型�。� 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：隨著互聯(lián)網(wǎng)用戶的急劇增長以及互聯(lián)網(wǎng)應(yīng)用的快速發(fā)展，現(xiàn)有的互聯(lián)網(wǎng)面臨著兩方面的問題：一是現(xiàn)有的骨干網(wǎng)絡(luò)鏈路帶寬已經(jīng)達到100Gbps的速度，要求路由器能夠提供與之相匹配的高性能報文轉(zhuǎn)發(fā)。二是隨著P2P、電子商務(wù)、證券電子化交易的不斷發(fā)展和完善，在網(wǎng)絡(luò)邊緣路由器中需要對大量的分組報文進行諸如加解密、流量整形、報文保序等一系列深度處理。 目前基于通用多核CPU的網(wǎng)絡(luò)處理器是業(yè)界研究的熱點，它將通用多核處理器和報文處理硬件加速引擎相結(jié)合，同時實現(xiàn)了報文的高速轉(zhuǎn)發(fā)及深度處理。多核多線程處理能夠很好的隱藏軟件DRAM訪問延遲并提供控制平面所需的高度編程靈活性。網(wǎng)絡(luò)加速引擎可以利用硬件的快速及并行特點，對實現(xiàn)了報文處理的快速路徑。然而，通用多核網(wǎng)絡(luò)處理器面臨著系統(tǒng)軟硬件I/O交互延遲較大的缺陷，限制了自身報文處理性能的提高。針對這一問題，，本文通過改進了原有基于通用多核網(wǎng)絡(luò)處理器的處理模型及訪存模型，提出了一種新型的基于通用多核的網(wǎng)絡(luò)處理器實現(xiàn)模型—Sandwich。主要工作和創(chuàng)新點包括： 1.深入分析了專用網(wǎng)絡(luò)處理器[2]及通用多核網(wǎng)絡(luò)處理器[1]的組成結(jié)構(gòu)及特點，將二者的報文處理模型和訪存模型進行了比較，認識到通用多核網(wǎng)絡(luò)處理器的性能瓶頸所在。Sandwich實現(xiàn)模型提出的報文處理模型能夠最大限度的減少報文處理過程中的軟硬件通信開銷，且大大減輕了軟件處理部分的負載。訪存模型能夠加速CPU對DRAM的訪問速度，并通過對整個報文的深度處理實現(xiàn)靈活的控制平面。 2.設(shè)計了FIB查表[4][5][7]過程在SandwichNP上的映射算法，將整個查表周期分為三個階段，分別映射到SandwichNP的輸入加速、軟件處理、輸出加速模塊中。算法中每次報文查表最多只需要一次軟件內(nèi)存訪問即可完成，且多線程處理能夠進一步隱藏查表時延。空間效率上看，軟硬件以極低的存儲開銷支持了大規(guī)模的核心路由器轉(zhuǎn)發(fā)表，且即使轉(zhuǎn)發(fā)表規(guī)�？焖僭鲩L也不會增加過多的額外存儲開銷。 3.在SandwichNP原型系統(tǒng)—GalaxyNP上實現(xiàn)了如上的Fib查表算法，并測得了真實網(wǎng)絡(luò)環(huán)境下的多線程報文I/O速率及報文轉(zhuǎn)發(fā)速率，實驗結(jié)果表明基于Sandwich的報文轉(zhuǎn)發(fā)速率及報文I/O速率能夠在任何參數(shù)設(shè)定下保持一致，并且隨著網(wǎng)絡(luò)鏈路帶寬的速度增長而增長，能夠保證多端口的10Gbps速率下的報文線速轉(zhuǎn)發(fā)。 綜上所述，本文針對通用多核網(wǎng)絡(luò)處理器報文處理所面臨的問題，提出了一種新型網(wǎng)絡(luò)處理器實現(xiàn)模型—Sandwich，該模型已經(jīng)成功應(yīng)用于基于自主CPU構(gòu)建的通用多核網(wǎng)絡(luò)處理器平臺上，其研究成果對提高通用多核網(wǎng)絡(luò)處理器的報文處理性能有一定的理論意義和實用價值。
[Abstract]:With the rapid growth of Internet users and the rapid development of Internet applications, the existing Internet is facing two problems: first, the existing backbone network link bandwidth has reached the speed of 100Gbps. Routers are required to provide matching high performance packet forwarding. Second, with the development and perfection of P2P, E-commerce and electronic securities trading, a series of advanced processing such as encryption and decryption, traffic shaping, message preservation and so on are needed in network edge routers. At present, the network processor based on general-purpose multi-core CPU is a hot topic in the industry. It combines the general-purpose multi-core processor with the packet processing hardware acceleration engine, and realizes the high-speed forwarding and deep processing of packets. Multi-core multithreading can hide the software DRAM access delay and provide high programming flexibility for the control plane. The network acceleration engine can take advantage of the fast and parallel characteristics of hardware to realize the fast path of packet processing. However, the general-purpose multicore network processor is faced with the disadvantage of large I / O interaction delay between hardware and software of the system, which limits the improvement of its packet processing performance. In order to solve this problem, this paper improves the processing model and memory access model based on general-purpose multi-core network processor, and proposes a new implementation model of network processor based on general-purpose multi-core network processor-Sandwich. Key areas of work and innovation include: 1. In this paper, the structure and characteristics of special network processor [2] and general multi-core network processor [1] are analyzed, and their message processing models and memory access models are compared. It is recognized that the packet processing model proposed by the performance bottleneck of the universal multi-core network processor. Sandwich implementation model can minimize the communication overhead between hardware and software in the process of packet processing and greatly reduce the load of the software processing part. The memory access model can accelerate the access speed of CPU to DRAM and realize the flexible control plane through the deep processing of the whole message. 2. The mapping algorithm of FIB lookup table [4] [5] [7] process on SandwichNP is designed. The whole lookup period is divided into three stages: input acceleration, software processing and output acceleration module of SandwichNP. In the algorithm, only one software memory access is required for every packet search, and multithread processing can further hide the lookup delay. In terms of spatial efficiency, hardware and software support large scale core router forwarding tables with very low storage overhead, and even if the forwarding table scale grows rapidly, it will not add too much extra storage overhead. 3. The above Fib lookup algorithm is implemented on the SandwichNP prototype system -Galaxy NP, and the I / O rate and the forwarding rate of multithreaded packets in real network environment are measured. The experimental results show that the packet forwarding rate and the I / O rate based on Sandwich can be consistent under any parameter setting, and increase with the increase of the network link bandwidth, which can guarantee the transmission of the line rate of the packet at the 10Gbps rate of multiple ports. To sum up, this paper aims at the problem of message processing in general multi-core network processor. A new network processor implementation model, -Sandwich, is proposed. The model has been successfully applied to a general multi-core network processor platform based on autonomous CPU. The research results have certain theoretical significance and practical value for improving the packet processing performance of universal multi-core network processors.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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