本文選題：前導(dǎo)零預(yù)測器 + 并行糾錯��； 參考：《西安電子科技大學(xué)》2016年碩士論文

【摘要】：一直以來,浮點運算能力對于微處理器性能的評估至關(guān)重要。隨著微電子技術(shù)的不斷發(fā)展,高性能的浮點乘加部件(Multiply-Add-Fused,MAF)和加法器在浮點運算單元的設(shè)計上,有著很高的地位。前導(dǎo)零預(yù)測器(Leading Zero Anticipation,LZA)并行于加法器工作,用于直接計算出浮點加法結(jié)果中首個1的位置,并通過前導(dǎo)零檢測器(Leading Zeros Detector,LZD)得到前導(dǎo)零數(shù)目。其對IEEE-754算術(shù)標(biāo)準(zhǔn)中所規(guī)定的浮點運算的規(guī)格化操作階段進行了優(yōu)化,是高性能加法電路和乘加電路中的關(guān)鍵部分。前導(dǎo)零預(yù)測器從預(yù)測結(jié)果的精確度上大致可分為兩種,一種是精確預(yù)測,一種是一位誤差預(yù)測。本文對前導(dǎo)零預(yù)測的算法與電路實現(xiàn)進行研究,設(shè)計并實現(xiàn)兩種不同結(jié)構(gòu)的精確前導(dǎo)零預(yù)測器,并對三操作數(shù)前導(dǎo)零預(yù)測器進行電路實現(xiàn)。本文的主要工作如下:首先,本文對基本的前導(dǎo)零預(yù)測算法進行介紹,描述了經(jīng)典的前導(dǎo)零預(yù)測器結(jié)構(gòu),實現(xiàn)了對加法結(jié)果中首1位置的預(yù)測。并結(jié)合乘加器結(jié)構(gòu),描述了前導(dǎo)零預(yù)測邏輯在傳統(tǒng)乘加器中的實現(xiàn)與應(yīng)用。但由于預(yù)測數(shù)位后序列碼型的不同情況,會導(dǎo)致1位預(yù)測誤差的產(chǎn)生,因此該預(yù)測器為非精確預(yù)測。然后,對精確前導(dǎo)零預(yù)測的算法進行研究,主要探討了并行糾錯和基于進位信號糾錯兩種前導(dǎo)零糾錯算法。并行糾錯算法在對預(yù)測出的首1位置序列進行檢測的同時,通過編碼樹電路每兩位檢測得到出錯碼型,最終得到糾錯信號,對規(guī)格化數(shù)目進行修正。基于進位信號糾錯利用加法器中對應(yīng)預(yù)測的結(jié)果中首個1位置的進位信號,對是否出現(xiàn)預(yù)測誤差進行判斷。同時,還描述了三操作數(shù)前導(dǎo)零預(yù)測算法。其次,本文實現(xiàn)了計算序列中前導(dǎo)零數(shù)目的前導(dǎo)零檢測器,其主要應(yīng)用于對首1位置預(yù)測序列的檢測。并分別基于并行糾錯前導(dǎo)零算法與進位糾錯前導(dǎo)零算法,實現(xiàn)兩種不同結(jié)構(gòu)的精確前導(dǎo)零預(yù)測器電路。對于并行糾錯前導(dǎo)零預(yù)測器結(jié)構(gòu),整個電路并行于加法器執(zhí)行,減小了電路延遲,提升了電路性能。對于進位糾錯的前導(dǎo)零預(yù)測器結(jié)構(gòu),利用加法器中的進位信號使整個電路邏輯簡單,整體的電路面積較小。之后,根據(jù)三操作數(shù)前導(dǎo)零預(yù)測算法,完成三操作數(shù)前導(dǎo)零預(yù)測器的電路設(shè)計。最后,本文對三種結(jié)構(gòu)進行對比,對各自的特點及適用情況進行分析。并通過VHDL硬件描述語言完成了上述三種結(jié)構(gòu)的電路描述,對電路進行了功能仿真,保證其功能的正確性。同時對其進行了邏輯綜合,檢測其電路性能。
[Abstract]:The floating-point computing ability is very important to evaluate the performance of microprocessor. With the development of microelectronic technology, the high performance floating-point multiplying and adding parts (Multiply-Add-FusedMAF) and adder play a very important role in the design of floating-point operation unit. The leading Zero precursor (LZA) works in parallel with the adder, which is used to calculate the position of the first 1 in the floating-point addition directly, and to obtain the number of leading zeros by leading Zeros detector LZD. It optimizes the standard operation stage of floating-point operation in IEEE-754 arithmetic standard and is the key part of high performance additive circuit and multiplication circuit. Leading zero predictors can be roughly divided into two types from the accuracy of prediction results, one is accurate prediction, the other is one bit error prediction. In this paper, the algorithm and circuit implementation of leading zero prediction are studied, two kinds of accurate leading zero predictors with different structures are designed and implemented, and the three operands leading zero predictors are implemented by circuit. The main work of this paper is as follows: first, this paper introduces the basic leading zero prediction algorithm, describes the classical structure of the leading zero predictor, and realizes the prediction of the first position in the addition result. The realization and application of leading zero predictive logic in traditional multiplier adder are described. However, due to the difference in the code types of the predicted digital sequence, the one-bit prediction error will be generated, so the predictor is an inexact predictor. Then, the algorithm of accurate leading zero prediction is studied, and two kinds of leading zero error correction algorithms based on carry signal and parallel error correction are mainly discussed. The parallel error correction algorithm detects the first position sequence of the first position, and obtains the error pattern by every two bit detection in the coding tree circuit. Finally, the error correction signal is obtained, and the normalized number is corrected. Based on the error-correction of carry signal, using the carry signal of the first 1 position in the corresponding prediction result in the adder, the prediction error is judged. At the same time, a three-Operand leading zero prediction algorithm is also described. Secondly, a leading zero detector for calculating the number of leading zeros in the sequence is implemented, which is mainly applied to the detection of the first position prediction sequence. Based on the parallel error correction leading zero algorithm and carry error correction leading zero algorithm, two kinds of accurate leading zero predictor circuits with different structures are implemented. For the parallel error correction leading zero predictor structure, the whole circuit is executed in parallel with the adder, which reduces the circuit delay and improves the circuit performance. For the leading zero predictor structure of carry error correction, the carry signal in the adder makes the whole circuit logic simple, and the whole circuit area is small. Then, according to the three-Operand leading zero prediction algorithm, the circuit design of the three-Operand leading zero predictor is completed. Finally, this paper compares the three structures and analyzes their characteristics and application. The circuit description of the above three structures is completed by VHDL hardware description language, and the functional simulation of the circuit is carried out to ensure the correctness of its function. At the same time, the logic synthesis is carried out, and the circuit performance is tested.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP332.2

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本文編號：1938911