本文選題：NAND + FLASH��； 參考：《國防科學(xué)技術(shù)大學(xué)》2011年碩士論文

【摘要】：隨著信息技術(shù)的高速發(fā)展,用戶對(duì)數(shù)據(jù)存儲(chǔ)容量和速度的要求不斷增加,大容量高可靠性存儲(chǔ)系統(tǒng)的要求給存儲(chǔ)領(lǐng)域帶來了挑戰(zhàn),而傳統(tǒng)計(jì)算機(jī)存儲(chǔ)系統(tǒng)采用的機(jī)械磁盤設(shè)備由于存儲(chǔ)量、I/O訪問延遲等問題成為限制存儲(chǔ)系統(tǒng)性能的瓶頸。與此同時(shí)閃存(FLASH)作為非易失性存儲(chǔ)介質(zhì)擁有讀寫速度快、數(shù)據(jù)非易失性好、存儲(chǔ)容量大、無機(jī)械機(jī)制、制造成本低廉、良好并行性潛力等特征,經(jīng)過逐步發(fā)展和多次技術(shù)變革,逐漸顯露出其巨大的優(yōu)勢(shì),受到了國內(nèi)外學(xué)者以及工業(yè)界的關(guān)注,未來或?qū)⑻娲鷤鹘y(tǒng)磁盤。 本文設(shè)計(jì)并實(shí)現(xiàn)了一個(gè)基于NAND FLASH的多路并行存儲(chǔ)系統(tǒng),以FPGA開發(fā)板為實(shí)驗(yàn)平臺(tái),使用三星公司的大容量NAND FLASH芯片為存儲(chǔ)單元構(gòu)建立多路并行存儲(chǔ)系統(tǒng),實(shí)驗(yàn)表明該系統(tǒng)具有良好的并行性、高速、可靠、安全等特點(diǎn)。論文的主要工作和創(chuàng)新包括: 1.對(duì)FLASH的相關(guān)技術(shù)和FLASH存儲(chǔ)的研究現(xiàn)狀進(jìn)行了詳細(xì)研究并提出建立NAND FLASH存儲(chǔ)系統(tǒng)的可能性,并分析了構(gòu)建系統(tǒng)的優(yōu)點(diǎn)以及會(huì)遇到的難題;通過對(duì)NAND FLASH芯片內(nèi)部結(jié)構(gòu)和接口詳細(xì)研究,提出了研究多路并行存儲(chǔ)系統(tǒng)的可行性和目標(biāo)。 2.根據(jù)FLASH芯片的結(jié)構(gòu)特點(diǎn),設(shè)計(jì)了基于NAND FLASH的多路并行存儲(chǔ)板卡,并以此板卡為基礎(chǔ)硬件完成了存儲(chǔ)系統(tǒng)的模塊設(shè)計(jì),包括主邏輯模塊設(shè)計(jì)、ECC模塊設(shè)計(jì)、交差開關(guān)模塊設(shè)計(jì)、亂序發(fā)射模塊設(shè)計(jì)。 3.實(shí)現(xiàn)了基于NAND FLASH的多路并行存儲(chǔ)系統(tǒng),完成了系統(tǒng)對(duì)數(shù)據(jù)讀、寫、刪除等操作的仿真,并在FPGA實(shí)驗(yàn)開發(fā)板上保證了系統(tǒng)對(duì)數(shù)據(jù)存取的正常運(yùn)行。通過FPGA實(shí)驗(yàn)平臺(tái)對(duì)系統(tǒng)進(jìn)行測(cè)試,在4*8G的FLASH卡上實(shí)現(xiàn)了600M+的存取速率。 4.針對(duì)大規(guī)模固態(tài)閃存系統(tǒng)引入多路并行技術(shù)帶來的壞塊問題,提出了一種高效壞塊管理策略,采取并行存儲(chǔ)壞塊編碼技術(shù)來節(jié)約壞塊表存儲(chǔ)空間,減少壞塊處理功耗,同時(shí)采取壞塊表重構(gòu)處理技術(shù)有效解決了系統(tǒng)中的同位置壞塊難題。對(duì)FLASH芯片的順序命令模式進(jìn)行理論研究,提出了基于亂序發(fā)射的FLASH命令執(zhí)行模型,并設(shè)計(jì)了基于亂序發(fā)射的NAND FLASH存儲(chǔ)控制器。
[Abstract]:With the rapid development of information technology, the requirement of data storage capacity and speed is increasing. The requirement of large capacity and high reliability storage system brings challenges to the storage field. The mechanical disk equipment used in the traditional computer storage system is a bottleneck to the performance of the storage system because of the storage capacity and the I / O access delay. At the same time flash memory as a non-volatile storage medium has the characteristics of fast reading and writing speed, good data non-volatile, large storage capacity, no mechanical mechanism, low manufacturing cost and good parallelism potential. It gradually shows its great advantage, and has attracted the attention of domestic and foreign scholars and industry, and will replace the traditional disk in the future. In this paper, a multi-channel parallel storage system based on NAND FLASH is designed and implemented. The FPGA development board is used as the experimental platform, and Samsung's large-capacity NAND FLASH chip is used to construct a multi-channel parallel storage system. Experiments show that the system has good parallelism, high speed, reliability and security. The main work and innovations of the thesis include: 1. The related technology of FLASH and the research status of FLASH storage are studied in detail, the possibility of establishing NAND FLASH storage system is put forward, and the advantages and difficulties of constructing NAND FLASH storage system are analyzed. Through the detailed study of the internal structure and interface of the NAND FLASH chip, the feasibility and goal of studying the multi-channel parallel memory system are put forward. 2. According to the structure characteristics of FLASH chip, a multi-channel parallel memory card based on NAND FLASH is designed, and the module design of the storage system is completed based on the card, including the design of main logic module and the design of alternating switch module. The design of random sequence emitter module. 3. A multi-channel parallel storage system based on NAND FLASH is implemented, and the system simulation of data reading, writing and deleting is completed, and the normal operation of data access is ensured on the FPGA experimental development board. The system is tested on the FPGA platform, and the 600m access rate is realized on the 4G FLASH card. 4. In order to solve the bad block problem caused by the introduction of multiplex parallel technology in large scale solid-state flash memory system, an efficient bad block management strategy is proposed, in which the memory space of bad block table is saved and the power consumption of bad block processing is reduced by adopting parallel memory bad block coding technology. At the same time, the bad block table reconstruction technology is adopted to solve the problem of the same location bad block effectively. In this paper, the sequential command mode of FLASH chip is studied theoretically, and a FLASH command execution model based on random sequence transmission is proposed, and a NAND FLASH memory controller based on random sequence transmission is designed.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2011
【分類號(hào)】：TP333

【引證文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前2條

1 姚銘;高密度高速存儲(chǔ)系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)[D];西安電子科技大學(xué);2013年

2 張帆;支持多種接口的數(shù)據(jù)存儲(chǔ)系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)[D];西安電子科技大學(xué);2013年

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本文編號(hào)：1930084