發(fā)布時間：2018-05-22 18:54

  本文選題：USB + IP核�。� 參考：《電子科技大學(xué)》2012年碩士論文

【摘要】：USB是英文(Universal Serial Bus)的縮寫，中文就是通用串行總線。USB是Intel聯(lián)合(Microsoft,IBM,康柏,NEC等)七家公司共同推出的總線標(biāo)準(zhǔn)，這是一種速度快、成本低、易于擴展的總線標(biāo)準(zhǔn)，同時也是目前電子產(chǎn)品中應(yīng)用最為廣泛的接口協(xié)議之一。支持設(shè)備即插即用和熱插拔功能的USB總線標(biāo)準(zhǔn)的出現(xiàn),對于信息產(chǎn)業(yè)和計算機的發(fā)展具有重大意義。鑒于USB廣泛的應(yīng)用及迅猛的發(fā)展和經(jīng)濟效益，本文設(shè)計了一個USB設(shè)備接口IP核,討論了設(shè)計思想和方法。 本論文主要討論了USB設(shè)備接口IP核的設(shè)計。根據(jù)復(fù)雜數(shù)字邏輯電路和系統(tǒng)設(shè)計思想,為了降低設(shè)計復(fù)雜度,經(jīng)過深入研究USB協(xié)議后，決定在設(shè)計中采用自頂向下(Top-Down)的設(shè)計方法；同時該IP核使用VerilogHDL編寫代碼,在設(shè)計中我們把時序邏輯電路和組合邏輯電路分開設(shè)計，這樣能夠使得設(shè)計思路更清晰同時也讓總體結(jié)構(gòu)便于理解；為了使設(shè)計更易于綜合，代碼編寫也必須遵循可綜合風(fēng)格并且注重跨時鐘域的問題。論文主要包括以下幾個方面： 1)首先學(xué)習(xí)和分析USB協(xié)議,分析協(xié)議標(biāo)準(zhǔn)和數(shù)據(jù)傳輸方式，根據(jù)學(xué)習(xí)到的協(xié)議內(nèi)容和分析結(jié)果提出基于FPGA的USB設(shè)備接口IP核的總體設(shè)計方案，然后劃分各功能模塊,劃分成五個模塊:UTMI、控制器、物理層、FIFO、存儲器接口和協(xié)議層。設(shè)計方案中最關(guān)鍵的三個模塊是物理層模塊、控制器模塊和協(xié)議層模塊。 2)用Verilog編寫RTL級代碼，完成各功能模塊的詳細設(shè)計。物理層模塊主要完成采樣異步數(shù)據(jù)流以及分離時鐘和數(shù)據(jù)，模擬差分信號和數(shù)字信號的轉(zhuǎn)換；控制器模塊完成USB設(shè)備的數(shù)據(jù)傳輸和枚舉；協(xié)議層模塊功能比較復(fù)雜，為了實現(xiàn)復(fù)雜的USB協(xié)議，使用了有限狀態(tài)機的設(shè)計方法，協(xié)議層主要完成數(shù)據(jù)的打包和解包等。 3)用ModelSim SE和QuartusⅡ軟件對USB設(shè)備接口IP核進行綜合仿真，對設(shè)備接口IP在FPGA硬件平臺上進行了驗證。在驗證過程中，使用USB HOUND軟件截取USB總線上的通信數(shù)據(jù)，然后對截取數(shù)據(jù)分析來驗證USB主機和設(shè)備接口的數(shù)據(jù)通信是否成功。 驗證結(jié)果表明，，該設(shè)計的USB設(shè)備接口IP核是符合USB協(xié)議規(guī)范要求的，能很好的實現(xiàn)USB數(shù)據(jù)通信的功能;如果想作為一個單獨的IP模塊嵌入到SoC系統(tǒng)設(shè)計中,還需要經(jīng)過更深層次和更專業(yè)的優(yōu)化,這里我們只討論了功能的實現(xiàn)。
[Abstract]:USB (Universal Serial bus) is a bus standard developed jointly by seven companies, Intel, Microsoft, IBM, Compaq, etc., which is a fast, low cost and easy to extend bus standard. It is also one of the most widely used interface protocols in electronic products. The emergence of USB bus standard which supports plug and play and hot plug function is of great significance to the development of information industry and computer. In view of the wide application, rapid development and economic benefit of USB, this paper designs an IP core of USB device interface, and discusses the design ideas and methods. This paper mainly discusses the design of USB device interface IP core. According to the design idea of complex digital logic circuit and system, in order to reduce the design complexity, after deeply studying the USB protocol, it is decided to adopt Top-Downtop-down design method in the design, and the IP core uses VerilogHDL to write code. In the design, we separate the sequential logic circuit from the combinational logic circuit, which can make the design thinking clearer and the overall structure easier to understand; in order to make the design easier to synthesize, Code writing must also follow an integrated style and focus on cross-clock domains. The paper mainly includes the following aspects: 1) studying and analyzing the USB protocol, analyzing the protocol standard and data transmission mode, according to the protocol content and the analysis result, putting forward the overall design scheme of USB device interface IP core based on FPGA, then dividing each function module. Divided into five modules: UTMI, controller, physical layer FIFO, memory interface and protocol layer. The three key modules in the design are physical layer module, controller module and protocol layer module. 2) write RTL level code with Verilog, complete the detailed design of each function module. Physical layer module mainly completes sampling asynchronous data flow and separating clock and data, analog differential signal and digital signal conversion; Controller module completes data transmission and enumeration of USB device; Protocol layer module has complex function. In order to realize the complex USB protocol, the design method of finite state machine (FSM) is used, and the protocol layer mainly completes the data packaging and unpacking. 3) the IP core of USB device interface is simulated by ModelSim SE and Quartus 鈪

本文編號：1923235