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  本文選題：USB2.0 + 時統(tǒng)�。� 參考：《電子科技大學(xué)》2012年碩士論文

【摘要】：USB（Universal Serial Bus）是一種應(yīng)用在計算機領(lǐng)域的新型接口技術(shù)，最早是由Compaq、Intel、Microsoft等多家公司于1994年11月共同提出的，其目的是簡化外設(shè)的連接過程，用USB來取代PC現(xiàn)有的各種外圍接口，使外設(shè)的連接具有單一化、即插即用、熱插拔等特點。它的出現(xiàn)使PC機接口的擴展變得更加容易，是計算機外設(shè)連接技術(shù)的重大變革。 本論文在深入細致分析USB2.0接口數(shù)據(jù)流模型、設(shè)備架構(gòu)和主機軟硬件的基礎(chǔ)上，選取適當(dāng)?shù)腉PS接收模塊和USB2.0接口芯片，采用單片機和CPLD可編程器件技術(shù)，設(shè)計了各級驅(qū)動程序，在一塊電路板上集成了GPS接收解碼、B碼時統(tǒng)解碼，能提供微秒級的秒同步、20周同步信號和0.1毫秒級的時間信息，能對時間源是否有效進行判斷顯示、實現(xiàn)了切換和自動守時的功能，使得時統(tǒng)解碼終端進一步小型化、智能化，成功地解決了移動設(shè)備獨立工作時的時間信息獲取問題。 主要內(nèi)容如下： 1．探討了USB2.0接口規(guī)范，分析了USB2.0接口數(shù)據(jù)流模型，研究了USB2.0接口設(shè)備架構(gòu)，以及USB2.0接口的主機軟硬件技術(shù)。通過上述研究分析，確立了基于USB2.0接口的小型時統(tǒng)終端的總體設(shè)計方案。 2．深入分析了基于USB2.0接口的小型時統(tǒng)終端所需的硬件結(jié)構(gòu)及原理，進行了基于USB2.0接口的小型時統(tǒng)終端的硬件系統(tǒng)方案設(shè)計。主要包括：硬件的選擇和組成，電原理圖設(shè)計，布線設(shè)計和電路板設(shè)計。 3．詳細研究了基于USB2.0接口的小型時統(tǒng)終端所需的軟件架構(gòu)及原理，進行了基于USB2.0接口的小型時統(tǒng)終端的軟件系統(tǒng)方案設(shè)計。主要包括：CPLD程序設(shè)計，，單片機固件程序設(shè)計，設(shè)備驅(qū)動程序設(shè)計。 4．對基于USB2.0接口的小型時統(tǒng)終端應(yīng)用情況和測試情況進行了詳細論述，研究了基于USB2.0接口的小型時統(tǒng)終端的接口定義、技術(shù)指標、軟硬件安裝、使用范圍和故障排除等，進行了測試方法、測試儀器的確認和測試結(jié)果的分析。
[Abstract]:USB (Universal Serial Bus) is a new type of interface technology used in the field of computer. It was first introduced in November 1994 by many companies such as Compaq, Intel, Microsoft and so on. The purpose is to simplify the connection process of peripherals and replace the existing peripheral interfaces of PC with USB, so that the connection of peripherals is simplification, plug and play, and hot plug. Its appearance makes it easier to expand the interface of PC, and it is a significant change in the connection technology of computer peripherals.
On the basis of analyzing the USB2.0 interface data flow model, the device architecture and the host software and hardware, this paper selects the appropriate GPS receiving module and the USB2.0 interface chip, uses the MCU and the CPLD programmable device technology to design the driver at all levels, and integrates the GPS reception and decoding on a circuit board, and the B code time decoding. It can provide the decoding of the B code. Microsecond synchronization, 20 week synchronization signal and 0.1 millisecond time information, can judge whether the time source is effective, and realize the function of switching and automatic punctuality, making the time decoding terminal further miniaturized and intelligentized, successfully solving the problem of time information acquisition in the mobile device's independent work.
The main contents are as follows:
1. the specification of USB2.0 interface is discussed, the data flow model of USB2.0 interface is analyzed, the USB2.0 interface device architecture and the host software and hardware technology of the USB2.0 interface are studied. Through the analysis, the overall design scheme of the small time series terminal based on the USB2.0 interface is established.
2. the hardware structure and principle of a small time series terminal based on USB2.0 interface are deeply analyzed. The design of the hardware system of a small time series terminal based on the USB2.0 interface is designed, including the selection and composition of the hardware, the electrical schematic design, the wiring design and the circuit board design.
3. the software architecture and principle of a small time series terminal based on USB2.0 interface are studied in detail, and the software system scheme of a small time series terminal based on USB2.0 interface is designed. It mainly includes: CPLD program design, single chip firmware program design, and device driver design.
4. the application and testing of the small time series terminal based on USB2.0 interface are discussed in detail. The interface definition, technical index, software and hardware installation, use range and troubleshooting of the small time series terminal based on USB2.0 interface are studied. The test method, the confirmation of the test instrument and the analysis of the test result are carried out.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP334.7

【參考文獻】

相關(guān)期刊論文 前1條

1 黃睿芳;;基于FPGA的時統(tǒng)模塊可靠性設(shè)計[J];電子技術(shù);2011年06期

本文編號：1920030