本文選題：高性能靜態(tài)存儲(chǔ)器 + 譯碼電路�。� 參考：《安徽大學(xué)》2013年碩士論文

【摘要】：隨著移動(dòng)互聯(lián)網(wǎng)技術(shù)的發(fā)展,嵌入式處理器和片上系統(tǒng)(SoC, System on a Chip)的速度不斷提高,從而推動(dòng)高速緩存(Cache)對速度的需求,作為高速緩存的核心部件,靜態(tài)隨機(jī)存儲(chǔ)器(SRAM, Static Random Access Memory)成為系統(tǒng)速度提升的關(guān)鍵。 本文基于高性能嵌入式處理器的需求進(jìn)行高速SRAM存儲(chǔ)器的相關(guān)理論模型、結(jié)構(gòu)優(yōu)化和關(guān)鍵電路的研究,著重分析和改進(jìn)現(xiàn)有高速SRAM的設(shè)計(jì)技術(shù)。高性能SRAM是指可以高速度工作的SRAM, SRAM的速度主要體現(xiàn)在地址輸入到數(shù)據(jù)讀出的延遲時(shí)間上,大小由從地址輸入到數(shù)據(jù)讀出的關(guān)鍵路徑上延遲決定,包括地址輸入緩沖、地址譯碼、字線選通、存儲(chǔ)單元、位線輸出、靈敏放大器及輸出緩沖的延遲等,針對以上延遲模塊,本文提出了一些優(yōu)化SRAM速度的技術(shù)和電路結(jié)構(gòu),具體有： 1、對譯碼電路的互連線引入分布rC模型進(jìn)行研究,結(jié)合工藝特性和傳統(tǒng)延遲模型,合理考慮導(dǎo)線寄生特性的影響,為譯碼器電路的優(yōu)化提供更精確的延遲模型。根據(jù)延遲優(yōu)化的理論模型可確定SRAM存儲(chǔ)器中譯碼電路的晶體管尺寸,從而實(shí)現(xiàn)高性能譯碼電路的設(shè)計(jì)及優(yōu)化。 2、高性能SRAM存儲(chǔ)器的核心部件是存儲(chǔ)單元,通常存儲(chǔ)單元決定了存儲(chǔ)器的系統(tǒng)結(jié)構(gòu)和穩(wěn)定性。本文提出非對稱六管存儲(chǔ)單元,采用分級(jí)讀操作形式,等比例增大讀支路的3個(gè)管子尺寸,并采用低閩值晶體管,從而增大讀支路的驅(qū)動(dòng)強(qiáng)度。另外,由于線寄生影響越來越大,采用位線分級(jí)的讀結(jié)構(gòu)比較適合工藝進(jìn)一步縮小的應(yīng)用。 3、采用位線分級(jí)的方式可以提高大容量SRAM的工作速度,本文在傳統(tǒng)位線分級(jí)的基礎(chǔ)上,通過從位線放電快慢的角度分析,推導(dǎo)出更加優(yōu)化的分級(jí)結(jié)構(gòu),可以減小位線電容,使得位線充放電更快,實(shí)現(xiàn)整體速度的提高。并在SMIC65nm工藝下設(shè)計(jì)了相應(yīng)電路并進(jìn)行仿真驗(yàn)證,從而論證了分析的正確性。 通過上述分析研究,最終建立一套高性能SRAM存儲(chǔ)器譯碼電路的延遲優(yōu)化模型和設(shè)計(jì)方法,結(jié)合非對稱六管存儲(chǔ)單元和優(yōu)化的位線分級(jí)技術(shù),基于SMIC65nm LL (low leakage)工藝,設(shè)計(jì)了一款高性能4Kb SRAM存儲(chǔ)器,經(jīng)仿真驗(yàn)證當(dāng)工作電壓在1.2V時(shí)后仿真的訪問時(shí)間為0.514ns,工作頻率達(dá)到1.5GHz。
[Abstract]:With the development of mobile Internet technology, the speed of embedded processors and on-chip systems (SoC, System on a Chip) is increasing, which promotes the speed requirement of cache, which is the core component of cache. Static random access memory (SRAM) and Static Random Access Memory) are the key to improve the speed of the system. Based on the requirement of high performance embedded processor, this paper studies the theoretical model, structure optimization and key circuits of high speed SRAM memory, and focuses on analyzing and improving the existing design technology of high speed SRAM. High performance SRAM refers to the SRAM, which can work at high speed. The speed of SRAM is mainly reflected in the delay time between address input and data readout, and the size is determined by the delay in the critical path from address input to data readout, including address input buffering. Address decoding, word line gating, memory cell, bit line output, sensitive amplifier and output buffer delay, etc., this paper presents some techniques and circuit structures to optimize SRAM speed. 1. The distributed RC model is introduced into the interconnection of the decoding circuit. Combining the process characteristic and the traditional delay model, the influence of the parasitic characteristic of the conductor is considered reasonably, which provides a more accurate delay model for the optimization of the decoder circuit. According to the theoretical model of delay optimization, the transistor size of decoding circuit in SRAM memory can be determined, and the design and optimization of high performance decoding circuit can be realized. 2. The core component of high performance SRAM memory is memory cell, which usually determines the system structure and stability of memory. In this paper, an asymmetric six-transistor memory cell is proposed, in which the three-tube size of the reading branch is increased in equal proportion and the low threshold transistor is used to increase the driving strength of the reading branch. In addition, because of the increasing influence of line parasitism, the reading structure with bit line classification is more suitable for further reduction of technology. 3. The speed of large capacity SRAM can be improved by using bit line classification. Based on the traditional bit line classification, this paper deduces a more optimized classification structure from the angle of bit line discharge speed and slowness, which can reduce the bit line capacitance. Make bit line charge and discharge faster, achieve the overall speed of the increase. The corresponding circuit is designed and verified by simulation in SMIC65nm process, and the correctness of the analysis is proved. Through the above analysis and research, a set of delay optimization model and design method of high performance SRAM memory decoding circuit are established, combined with asymmetric six-transistor memory cell and optimized bit-line grading technology, based on SMIC65nm LL low leak process. A high performance 4Kb SRAM memory is designed. The simulation results show that the simulated access time is 0.514 ns and the operating frequency is 1.5 GHz when the working voltage is 1.2 V.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333

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本文編號(hào)：1917254