本文選題：非易失性 + OTP存儲(chǔ)器　； 參考：《蘇州大學(xué)》2013年碩士論文

【摘要】：本文基于eMemory公司的邏輯工藝OTP單元，設(shè)計(jì)了一個(gè)存儲(chǔ)密度為1K×13bits的OTP存儲(chǔ)器，數(shù)據(jù)寬度為16bits，工作電壓范圍為2V到5.5V，電源電壓3V以上時(shí)讀取時(shí)間不超過(guò)100ns，編程時(shí)間不超過(guò)30μs，讀取電流不超過(guò)2mA，靜態(tài)電流典型值為1μA。 本文首先介紹了OTP存儲(chǔ)器的發(fā)展背景和研究進(jìn)展。然后分析了OTP存儲(chǔ)單元的工作機(jī)制，，對(duì)比研究了兩種存儲(chǔ)陣列結(jié)構(gòu)，完成了內(nèi)核架構(gòu)的設(shè)計(jì)。在電路設(shè)計(jì)方面，本文詳細(xì)介紹了OTP存儲(chǔ)器各功能模塊的工作原理及設(shè)計(jì)方法，重點(diǎn)設(shè)計(jì)了電路電壓產(chǎn)生模塊，采用帶隙基準(zhǔn)電路來(lái)對(duì)電源電壓進(jìn)行校準(zhǔn)得到讀取電壓，同時(shí)完成了對(duì)各個(gè)模塊仿真與分析。接著本文根據(jù)設(shè)計(jì)原理圖完成了整體電路的版圖設(shè)計(jì)和整體電路的讀寫(xiě)仿真。最后對(duì)整體設(shè)計(jì)過(guò)程中遇到的幾個(gè)重點(diǎn)問(wèn)題進(jìn)行了分析和解決。 本課題是在0.18μm標(biāo)準(zhǔn)CMOS工藝5V器件模型上完成的設(shè)計(jì)，目前國(guó)內(nèi)較少報(bào)道。本次設(shè)計(jì)的OTP存儲(chǔ)器IP在成本和工藝復(fù)雜度等方面都具有優(yōu)勢(shì)，而且可以滿足2V到5.5V的電源電壓工作范圍。
[Abstract]:Based on the logical process OTP unit of eMemory Company, a OTP memory with storage density of 1K 脳 13bits is designed in this paper. The data width is 16 bits, the working voltage range is from 2 V to 5.5 V, the reading time is not more than 100 ns, the programming time is not more than 30 渭 s, the reading current is not more than 2 Ma, the typical static current is 1 渭 A. This paper first introduces the development background and research progress of OTP memory. Then, the working mechanism of OTP memory cell is analyzed, two storage array structures are compared and the kernel architecture is designed. In the aspect of circuit design, this paper introduces the working principle and design method of each function module of OTP memory in detail. The circuit voltage generation module is designed emphatically. The bandgap reference circuit is used to calibrate the power supply voltage to get the read voltage. At the same time, the simulation and analysis of each module are completed. Then, according to the schematic diagram, the layout of the whole circuit and the simulation of the whole circuit are completed. Finally, several key problems encountered in the whole design process are analyzed and solved. The design of 5V device model based on 0.18 渭 m standard CMOS process is presented in this paper. The OTP memory IP designed in this paper has advantages in cost and process complexity, and can meet the operating range of 2V to 5.5V power supply voltage.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333;TN402

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本文編號(hào)：1917106