本文選題：系統(tǒng)仿真 + 協(xié)同式��； 參考：《解放軍信息工程大學(xué)》2013年碩士論文

【摘要】：隨著微電子技術(shù)的快速發(fā)展，新型體系架構(gòu)處理器不斷涌現(xiàn)，應(yīng)用軟件資源稀缺問題凸顯。將占市場主導(dǎo)地位的X86架構(gòu)應(yīng)用軟件資源移植到新型處理器上，是實現(xiàn)新型處理器應(yīng)用普及的有效途徑。軟硬件協(xié)同式X86系統(tǒng)仿真技術(shù)能夠有效解決“代碼移植”和體系結(jié)構(gòu)兼容性的問題，通過引入適當硬件實現(xiàn)部分，使得軟件部分和硬件部分協(xié)同工作，有效提升X86系統(tǒng)仿真性能，已成為新型處理器應(yīng)用的重要支撐技術(shù)。 本文深入分析制約X86系統(tǒng)仿真性能的關(guān)鍵瓶頸，對各仿真功能模塊進行了軟硬件劃分，提出了軟硬件協(xié)同式X86系統(tǒng)仿真模型，構(gòu)建了以開源處理器OpenRISC平臺為宿主機的X86系統(tǒng)仿真架構(gòu)Co-AB�；贔PGA和OpenRISC SoPC平臺，對Co-AB進行了測試與驗證；設(shè)計并實現(xiàn)了HardTLB及其訪問擴展指令，通過嵌入式匯編指令，使SoftMMU和HardTLB協(xié)同工作，提升了訪存指令中虛實地址轉(zhuǎn)換的仿真效率；提出了一種流水式指令譯碼仿真機制，設(shè)計并實現(xiàn)了流水式指令譯碼仿真部件，相對于指令串行譯碼仿真機制，有效減少了指令譯碼仿真的時間開銷。 實驗測試結(jié)果表明，，本文所設(shè)計的協(xié)同式VMMU部件和流水式指令譯碼仿真部件能夠正確地完成地址映射和指令譯碼仿真工作。協(xié)同式VMMU部件相比于傳統(tǒng)軟件實現(xiàn)方式可獲得36.7%的訪存性能提升；流水式譯碼機制相對于串行譯碼機制可以有效降低指令譯碼時間開銷大約41.8%。
[Abstract]:With the rapid development of microelectronics, new architecture processors are emerging. It is an effective way to popularize the application of X86 architecture. Hardware / software co-X86 system simulation technology can effectively solve the problems of "code transplantation" and architecture compatibility. By introducing appropriate hardware implementation part, the software and hardware parts can work together. Improving the performance of X86 system simulation effectively has become an important supporting technology for new processor applications. In this paper, the key bottleneck that restricts the performance of X86 system simulation is deeply analyzed, the software and hardware of each simulation function module are divided, and the simulation model of hardware / software co-X86 system is proposed. An X86 system simulation architecture based on open source processor OpenRISC platform is constructed. Based on the platform of FPGA and OpenRISC SoPC, the Co-AB is tested and verified, and the HardTLB and its access extension instruction are designed and implemented. Through the embedded assembly instruction, SoftMMU and HardTLB work together, and the simulation efficiency of virtual address translation in memory access instruction is improved. A pipelined instruction decoding simulation mechanism is proposed. A pipelined instruction decoding simulation unit is designed and implemented. Compared with the instruction serial decoding simulation mechanism, the time cost of instruction decoding simulation is effectively reduced. The experimental results show that the cooperative VMMU part and the pipelined instruction decoding simulation unit designed in this paper can correctly accomplish the address mapping and instruction decoding simulation. Compared with the traditional software implementation, the cooperative VMMU module can achieve 36.7% memory access performance, and the pipelined decoding mechanism can effectively reduce the instruction decoding time cost about 41.8% compared with the serial decoding mechanism.
【學(xué)位授予單位】：解放軍信息工程大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TP311.1

【參考文獻】

相關(guān)碩士學(xué)位論文 前1條

1 易海峰;復(fù)雜指令集快速譯碼設(shè)計[D];西北工業(yè)大學(xué);2005年

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