本文選題：多核 + 眾核　； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：多核是當(dāng)前微處理器的發(fā)展潮流。隨著工藝尺寸不斷減小,單位面積內(nèi)可集成的晶體管密度來(lái)越來(lái)越大,集成在單個(gè)片上的核數(shù)也越來(lái)越多。受到面積、功耗的制約,多核處理器在向眾核千核方向擴(kuò)展時(shí),對(duì)存儲(chǔ)系統(tǒng)的要求越來(lái)越高,如何構(gòu)建延時(shí)更小、容量更大、帶寬更大的片上存儲(chǔ)結(jié)構(gòu)成為發(fā)展眾核千核處理器的關(guān)鍵問題。三維集成電路技術(shù)通過采用TSV通孔可將多個(gè)die堆疊在一個(gè)芯片上,從而提高集成度,減小芯片內(nèi)互連延遲和功耗,可極大地?cái)U(kuò)展片上存儲(chǔ)結(jié)構(gòu)的設(shè)計(jì)空間。e DRAM技術(shù)采用邏輯兼容工藝可將DRAM單元集成在芯片上,比SRAM技術(shù)擁有更大存儲(chǔ)密度,更低的功耗,在大容量下?lián)碛懈〉脑L問延遲,可用于構(gòu)建片上高速大容量cache。結(jié)合三維集成電路技術(shù)和e DRAM技術(shù),可有效地解決多核處理器在向眾核千核處理器發(fā)展過程中面臨的存儲(chǔ)問題。本文介紹了常見的片上存儲(chǔ)結(jié)構(gòu)模型。CACTI是一款性能優(yōu)良的存儲(chǔ)器延遲、功耗、面積模擬器。本文利用改進(jìn)后的CACTI 6.5研究了e DRAM cache的特性,提出了基于e DRAM的高度可擴(kuò)展的存儲(chǔ)模型HSCM2。Mc PAT是一款流行的多核處理器功耗、面積和時(shí)序模擬器。為了使之可以可更貼近實(shí)際處理器的設(shè)計(jì),本文修改了Mc PAT,并利用修改的Mc PAT展開可擴(kuò)展的多核眾核片上存儲(chǔ)模型M2SM2設(shè)計(jì),并向三維進(jìn)行了擴(kuò)展,提出了兩種3D M2SM2結(jié)構(gòu)模型3D M2SM2-A和3D M2SM2-B。本文介紹了TSV的電氣特性,提出了用于建模TSV的面積、功耗和時(shí)序模型。本文提出了一個(gè)簡(jiǎn)單的三維處理器模型,本文將Mc PAT修改為3D Mc PAT,添加了對(duì)三維處理器模型的支持。本文最后利用3D Mc PAT對(duì)兩種3D M2SM2模型的面積、功耗展開了研究,指出采用更先進(jìn)的工藝、使用硬件復(fù)雜度較低的核、采用e DRAM技術(shù)和三維集成電路技術(shù)、采用層次更多的片上存儲(chǔ)結(jié)構(gòu)是未來(lái)多核眾核處理器的發(fā)展趨勢(shì)。
[Abstract]:Multi-core is the current trend of microprocessor development. As the process size decreases, the number of cores integrated on a single chip increases with the increasing density of integrated transistors per unit area. Restricted by the area and power consumption, the multi-core processor demands more and more storage system when it expands to the multi-core thousand core, so how to build the memory system with less delay and larger capacity. More bandwidth on-chip memory architecture has become a key issue in the development of multi-core thousand-core processors. Three-dimensional integrated circuit technology can stack multiple die on a single chip by adopting TSV holes, so as to improve integration and reduce interconnect delay and power consumption. The design space. E DRAM, which can greatly expand the on-chip memory structure, can integrate DRAM cells on the chip with a logical compatible process, which has greater memory density, lower power consumption and smaller access latency under large capacity than SRAM technology. Can be used to build on-chip high-speed large-capacity cache. Combined with 3D integrated circuit technology and e DRAM technology, the storage problem faced by multi-core processors in the development of multi-core Thousand core processors can be effectively solved. This paper introduces the common on-chip memory architecture model. CACTI is a memory delay, power consumption, area simulator with good performance. In this paper, we use the improved CACTI 6.5 to study the characteristics of e DRAM cache, and propose a highly extensible storage model based on e DRAM, HSCM2.Mc PAT, which is a popular multi-core processor power, area and timing simulator. In order to make it more close to the design of real processor, this paper modified MC path, expanded the extensible multi-core storage model M2SM2 design by using modified MC PAT, and extended it to 3D. Two 3D M2SM2 models, 3D M2SM2-A and 3D M2SM2-B, are proposed. This paper introduces the electrical characteristics of TSV and presents an area, power and timing model for modeling TSV. In this paper, a simple 3D processor model is proposed. In this paper, the Mc PAT is modified to 3D MC processor, and the support for 3D processor model is added. Finally, using 3D MC PAT to study the area and power consumption of two 3D M2SM2 models, it is pointed out that using more advanced technology, using the kernel with lower hardware complexity, using e DRAM technology and 3D integrated circuit technology. It is the development trend of multi-core processor in the future to adopt more hierarchical on-chip memory structure.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333
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本文編號(hào)：1876832