本文選題：SystemC + NAND�。� 參考：《哈爾濱工程大學(xué)》2013年碩士論文

【摘要】：隨著移動(dòng)終端設(shè)備、高可靠性存儲(chǔ)及高性能存儲(chǔ)服務(wù)等應(yīng)用對(duì)于體積小、重量輕、零噪聲、高可靠性存儲(chǔ)器的需求日趨強(qiáng)烈，基于NAND Flash型器件的存儲(chǔ)設(shè)備在存儲(chǔ)市場(chǎng)中占據(jù)越來(lái)越重要的地位。NAND Flash控制器實(shí)現(xiàn)對(duì)存儲(chǔ)芯片的存取訪問(wèn)控制及差錯(cuò)控制等功能，在當(dāng)前的單芯片系統(tǒng)中嵌入式NAND Flash控制器對(duì)于提高芯片集成度、降低系統(tǒng)成本和提高可靠性等都具有重要的意義。本文設(shè)計(jì)并實(shí)現(xiàn)了具有差錯(cuò)控制功能的NAND Flash控制器IP核，提出基于SystemC的交易級(jí)驗(yàn)證方案對(duì)所設(shè)計(jì)的NAND Flash控制器進(jìn)行了功能驗(yàn)證。 本文首先針對(duì)美光公司的NAND Flash型存儲(chǔ)器芯片MT29F4G08AAA設(shè)計(jì)了控制器IP核。通過(guò)分析NAND Flash的接口信號(hào)和操作時(shí)序，將每項(xiàng)操作拆分為幾種基本的子操作，，主要包括寫命令操作、寫地址操作、讀數(shù)據(jù)操作和寫數(shù)據(jù)操作，執(zhí)行一項(xiàng)或多項(xiàng)子操作來(lái)完成對(duì)NAND Flash的數(shù)據(jù)訪問(wèn)。為提高數(shù)據(jù)的可靠性，設(shè)計(jì)了ECC （ErrorCorrecting Code）模塊，通過(guò)對(duì)寫入和讀出NAND Flash的數(shù)據(jù)進(jìn)行差錯(cuò)控制編碼，實(shí)現(xiàn)檢測(cè)多位錯(cuò)并糾正一位錯(cuò)的功能�；谙到y(tǒng)級(jí)描述及驗(yàn)證語(yǔ)言SystemC，搭建了NANDFlash控制器的交易級(jí)驗(yàn)證環(huán)境，對(duì)所設(shè)計(jì)的NAND Flash控制器進(jìn)行了較為完備的驗(yàn)證。 利用ModelSim實(shí)現(xiàn)了Verilog HDL和SystemC的混合仿真，通過(guò)分析生成的波形圖和仿真數(shù)據(jù)，實(shí)現(xiàn)了對(duì)NAND Flash控制器IP核的系統(tǒng)級(jí)功能驗(yàn)證。論文工作表明，基于SystemC的交易級(jí)驗(yàn)證技術(shù)可以達(dá)到在系統(tǒng)設(shè)計(jì)初期同時(shí)開(kāi)展驗(yàn)證工作的目的，在驗(yàn)證效率上相對(duì)于RTL級(jí)驗(yàn)證也有顯著的提升。
[Abstract]:With the application of mobile terminal equipment , high - reliability storage and high - performance storage service , the need for small volume , light weight , zero noise and high reliability memory is becoming more and more intense . The NAND Flash controller plays an increasingly important role in the storage market . The NAND Flash controller designs and implements the NAND Flash controller IP core with error control function , and proposes a system C based transaction level verification scheme to verify the designed NAND Flash controller .

In order to improve the reliability of the data , an ECC ( ErrorCode Code ) module is designed to realize the detection of multiple dislocations and correct a fault . Based on the system level description and the verification language SystemC , the transaction level verification environment of the NAND Flash controller is built , and the designed NAND Flash controller is validated .

The mixed simulation of verilog HDL and SystemC is realized by ModelSim . The system level function verification of the NAND Flash controller IP core is realized by analyzing the generated waveform chart and the simulation data . The work of the paper shows that the transaction level verification technology based on SystemC can achieve the purpose of carrying out verification work at the same time in the early stage of the system design , and the verification efficiency is obviously improved with respect to RTL level verification .

【學(xué)位授予單位】：哈爾濱工程大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333

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