發(fā)布時(shí)間：2018-05-05 18:03

  本文選題：FPGA + 多核處理器�。� 參考：《燕山大學(xué)》2013年碩士論文

【摘要】：近年來，測試測量領(lǐng)域中需要進(jìn)行大數(shù)據(jù)量處理的情況越來越多，一些復(fù)雜測試系統(tǒng)對于數(shù)據(jù)處理的實(shí)時(shí)性和準(zhǔn)確性要求越來越高。目前多數(shù)的處理器，如單片機(jī)、數(shù)字信號(hào)處理器DSP等已無法滿足人們的需求。現(xiàn)場可編程門陣列FPGA作為嵌入式SOC設(shè)計(jì)的載體，具有體積小、功耗低、可靠性好的優(yōu)點(diǎn)，基于FPGA的多核處理器系統(tǒng)可實(shí)現(xiàn)系統(tǒng)的協(xié)同工作，可有效解決測試測量領(lǐng)域中多通道數(shù)據(jù)采集和海量數(shù)據(jù)并行處理等問題。 本文以Xilinx Spartan-3E開發(fā)板為設(shè)計(jì)平臺(tái)，運(yùn)用Xilinx ISE軟件和EDK套件，實(shí)現(xiàn)以32位軟核MicroBlaze為處理器模塊的片上多核互連的總體設(shè)計(jì)、硬件設(shè)計(jì)、核間通信的軟件測試以及單核與多核系統(tǒng)性能對比。主要工作如下： 設(shè)計(jì)一種采用FSL總線進(jìn)行核間通信的單PLB總線方式的多核系統(tǒng)結(jié)構(gòu)來優(yōu)化資源利用率，提高核間傳輸速度；利用ISE軟件在Spartan-3E開發(fā)板上創(chuàng)建自定義FIFO，將自定義FIFO作為核間通信機(jī)制，在Xilinx平臺(tái)工作室XPS中搭建多核系統(tǒng)硬件平臺(tái)，并完成對硬件的配置。 基于搭建的硬件系統(tǒng)平臺(tái)，借助Xilinx SDK中在線調(diào)試工具XMD，通過在多核上添加測試程序?qū)崿F(xiàn)系統(tǒng)通信結(jié)果顯示；利用邏輯分析儀Chipscope Pro追蹤FPGA內(nèi)部信號(hào)實(shí)現(xiàn)片內(nèi)調(diào)試。 為實(shí)現(xiàn)對單核與多核系統(tǒng)性能的客觀評價(jià)，從算法執(zhí)行時(shí)間和資源占用率兩方面考慮，，分析結(jié)果表明多核系統(tǒng)由于采用并行環(huán)路體系，并摒棄單核阻塞狀態(tài)下的等待時(shí)間，可以達(dá)到處理時(shí)間上的優(yōu)化；而多核系統(tǒng)的資源占用率較單核要高些。
[Abstract]:In recent years, there are more and more cases in the field of testing and measurement that need to be processed with large amount of data. Some complex test systems require more and more real-time and accuracy of data processing. At present, most processors, such as single chip computer, digital signal processor (DSP), can not meet the needs of people. As the carrier of embedded SOC design, field programmable gate array (FPGA) has the advantages of small volume, low power consumption and good reliability. The multi-core processor system based on FPGA can realize the cooperative work of the system. It can effectively solve the problems of multi-channel data acquisition and mass data parallel processing in the field of test and measurement. In this paper, Xilinx Spartan-3E development board is used as design platform, Xilinx ISE software and EDK suite are used to realize the overall design and hardware design of multi-core interconnection on chip with 32-bit soft core MicroBlaze as processor module. Software testing for intercore communication and performance comparison between single core and multi-core systems. The main tasks are as follows: A multi-core system structure based on single PLB bus with FSL bus for inter-core communication is designed to optimize the utilization of resources and improve the transmission speed between cores. The self-defined FIFO is created on the Spartan-3E development board by using ISE software. The self-defined FIFO is used as the communication mechanism between cores. The multi-core system hardware platform is built in the XPS of Xilinx platform studio, and the hardware configuration is completed. Based on the hardware system platform and with the help of the on-line debugging tool XMD in Xilinx SDK, the system communication results are displayed by adding test program to the multi-core, and the on-chip debugging is realized by using the logic analyzer Chipscope Pro to track the internal signal of FPGA. In order to evaluate the performance of single-core system and multi-core system objectively, the algorithm execution time and resource occupancy are considered. The results show that the multi-core system adopts parallel loop system and abandons the waiting time in single-core blocking state. The processing time can be optimized, and the resource occupancy of multi-core system is higher than that of single core system.
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 辛君君;黃松嶺;劉立力;趙偉;;基于FPGA的超多通道高速數(shù)據(jù)采集系統(tǒng)設(shè)計(jì)[J];電測與儀表;2008年10期

2 李平;廖永波;阮愛武;李威;李文昌;;SoC軟硬件協(xié)同技術(shù)的FPGA芯片測試新方法[J];電子科技大學(xué)學(xué)報(bào);2009年05期

3 李慶誠,張杰,湯建軍;FSL總線IP核及其在MicroBlaze系統(tǒng)中的應(yīng)用[J];單片機(jī)與嵌入式系統(tǒng)應(yīng)用;2005年06期

4 唐思章 ,黃勇;SoPC與嵌入式系統(tǒng)軟硬件協(xié)同設(shè)計(jì)[J];單片機(jī)與嵌入式系統(tǒng)應(yīng)用;2005年12期

5 曹政才;趙應(yīng)濤;王光國;;基于DSP+FPGA的高速通用實(shí)時(shí)信號(hào)處理平臺(tái)設(shè)計(jì)[J];電氣電子教學(xué)學(xué)報(bào);2010年02期

6 王德勝;康令州;;基于FPGA的實(shí)時(shí)圖像采集與預(yù)處理[J];電視技術(shù);2011年03期

7 何賓;王瑜;;基于Xilinx MicroBlaze多核嵌入式系統(tǒng)的設(shè)計(jì)[J];電子設(shè)計(jì)工程;2011年13期

8 張洋;;虞志益:引領(lǐng)多核處理器創(chuàng)新之路[J];中國發(fā)明與專利;2013年01期

9 鞠道霖;;雙核還不夠——英特爾四核平臺(tái)石破天驚[J];個(gè)人電腦;2006年11期

10 張饒;武曉島;謝學(xué)軍;;透過專利看微處理器的技術(shù)發(fā)展(四)——中國專利中的多核技術(shù)演進(jìn)分析[J];中國集成電路;2009年04期

相關(guān)碩士學(xué)位論文 前3條

1 王瑜;基于SOPC的多核處理器互連技術(shù)的研究[D];北京化工大學(xué);2011年

2 孫強(qiáng);基于JTAG和FPGA的嵌入式SOC驗(yàn)證系統(tǒng)研究與設(shè)計(jì)[D];合肥工業(yè)大學(xué);2009年

3 王佳豪;Mutek在MicroBlaze多核平臺(tái)上的實(shí)現(xiàn)[D];上海交通大學(xué);2008年

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