基于Han-Carlson結(jié)構(gòu)的加法器優(yōu)化設(shè)計(jì)
發(fā)布時(shí)間:2018-05-04 12:32
本文選題:并行前綴加法器 + Han-Carlson結(jié)構(gòu); 參考:《微電子學(xué)與計(jì)算機(jī)》2017年03期
【摘要】:Han-Carlson結(jié)構(gòu)是介于Kogge-Stone結(jié)構(gòu)和Brent-Kung結(jié)構(gòu)之間的一種并行前綴加法器,并且結(jié)合了兩種結(jié)構(gòu)的優(yōu)勢.基于Han-Carlson結(jié)構(gòu)并行前綴加法器,對(duì)其結(jié)構(gòu)特點(diǎn)進(jìn)行研究分析,在延時(shí)和面積上進(jìn)行折中選擇,提出了一種優(yōu)化方案,犧牲部分延時(shí),減少使用面積以降低功耗.將其與未優(yōu)化的Han-Carlson加法器以及混合加法器進(jìn)行對(duì)比后表明,該優(yōu)化方案成功減少了使用面積,降低了功耗.
[Abstract]:The Han-Carlson structure is a parallel prefix adder between the Kogge-Stone structure and the Brent-Kung structure, and combines the advantages of the two structures. Based on the parallel prefix adder of Han-Carlson structure, the characteristics of the parallel prefix adder are studied and analyzed, and the tradeoff between delay and area is selected. An optimization scheme is proposed to reduce power consumption by sacrificing partial delay and reducing usage area. The comparison with the unoptimized Han-Carlson adder and the hybrid adder shows that the proposed scheme can reduce the area and power consumption successfully.
【作者單位】: 電子科技大學(xué)電子科學(xué)技術(shù)研究院;
【分類號(hào)】:TP332.21
,
本文編號(hào):1843076
本文鏈接:http://sikaile.net/kejilunwen/jisuanjikexuelunwen/1843076.html
最近更新
教材專著