本文選題：嵌入式硬件系統(tǒng) + FPGA��； 參考：《華中科技大學(xué)》2012年碩士論文

【摘要】：隨著第六次火車提速，主要干線開始以時(shí)速200千米每小時(shí)的高速運(yùn)行，火車運(yùn)行控制系統(tǒng)安全性越來越重要，，機(jī)車之間的數(shù)據(jù)通信越來越頻繁。計(jì)算機(jī)技術(shù)在機(jī)車車輛上的應(yīng)用越來越多，列車通信網(wǎng)絡(luò)及主動(dòng)控制成為高速列車控制中不可或缺的關(guān)鍵技術(shù)。隨著微電子技術(shù)、計(jì)算機(jī)技術(shù)、數(shù)字傳輸技術(shù)的飛速發(fā)展，自行設(shè)計(jì)并實(shí)現(xiàn)安全穩(wěn)定列車通信網(wǎng)絡(luò)設(shè)備需求越來越大。 本文介紹了基于嵌入式系統(tǒng)的MVB和HDLC通信模塊硬件系統(tǒng)的設(shè)計(jì)，該系統(tǒng)用于實(shí)現(xiàn)列車通信網(wǎng)絡(luò)（TCN）協(xié)議規(guī)定的MVB總線數(shù)據(jù)通信和HDLC總線數(shù)據(jù)通信。該硬件系統(tǒng)平臺(tái)包含大容量存儲(chǔ)器、高性能處理器以及多種常用外圍總線接口，以此為硬件開發(fā)平臺(tái)可實(shí)現(xiàn)多種總線數(shù)據(jù)的交互。 論文分析火車運(yùn)行環(huán)境，確定硬件系統(tǒng)運(yùn)行的工作環(huán)境溫度范圍以及抗震性和防雷擊設(shè)計(jì)；對(duì)比不同處理器之間差異，選擇ARM作為本系統(tǒng)的核心處理器，設(shè)計(jì)采用FPGA+ARM硬件平臺(tái)方案；簡要說明MVB總線及HDLC總線對(duì)硬件接口的需求；論文采用大量的篇幅對(duì)系統(tǒng)的總體結(jié)構(gòu)設(shè)計(jì)、硬件模塊設(shè)計(jì)、總線接口設(shè)計(jì)以及硬件調(diào)試進(jìn)行詳盡的論述。 經(jīng)過大量的分析和設(shè)計(jì)工作，本文實(shí)現(xiàn)MVB總線及HDLC總線單板設(shè)計(jì)工作。同時(shí)，系統(tǒng)通過CAN總線以及RS485總線實(shí)現(xiàn)與其他設(shè)備進(jìn)行數(shù)據(jù)交互。本系統(tǒng)已順利通過項(xiàng)目驗(yàn)收，系統(tǒng)工作穩(wěn)定，性能可靠，各項(xiàng)指標(biāo)都滿足要求。
[Abstract]:With the increase of the speed of the sixth train, the main trunk lines begin to run at a high speed of 200 km / h. The safety of the train operation control system is becoming more and more important, and the data communication between locomotives is becoming more and more frequent. The application of computer technology in locomotive and rolling stock is more and more. Train communication network and active control have become the indispensable key technology in high-speed train control. With the rapid development of microelectronic technology, computer technology and digital transmission technology, the demand for designing and implementing safe and stable train communication network equipment is increasing. This paper introduces the design of the hardware system of MVB and HDLC communication module based on embedded system. The system is used to realize the MVB bus data communication and HDLC bus data communication stipulated in the train communication network. The hardware platform consists of large capacity memory, high performance processor and a variety of common peripheral bus interfaces. This hardware development platform can realize the interaction of many kinds of bus data. This paper analyzes the running environment of the train, determines the temperature range of the operating environment of the hardware system, and the design of seismic resistance and lightning protection, compares the differences between different processors, and selects ARM as the core processor of the system. The hardware platform of FPGA ARM is adopted, the requirement of MVB bus and HDLC bus for hardware interface is briefly explained, the overall structure of the system and the hardware module are designed with a large number of pages. Bus interface design and hardware debugging are discussed in detail. After a lot of analysis and design work, this paper realizes the design of MVB bus and HDLC bus single board. At the same time, the system interacts with other devices through CAN bus and RS485 bus. This system has passed the project acceptance smoothly, the system work stably, the performance is reliable, each index all satisfies the request.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TN919.72;TP368.1

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相關(guān)期刊論文 前2條

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本文編號(hào)：1836305