SIMD DSP中的高性能定點(diǎn)算術(shù)運(yùn)算部件的設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間:2018-04-25 08:11
本文選題:銀河飛騰邁創(chuàng) + SIMD; 參考:《國(guó)防科學(xué)技術(shù)大學(xué)》2012年碩士論文
【摘要】:在視頻圖像處理、雷達(dá)信號(hào)處理和無(wú)線(xiàn)通信等嵌入式計(jì)算領(lǐng)域,由于處理數(shù)據(jù)量較大、數(shù)據(jù)并行性高,對(duì)數(shù)據(jù)計(jì)算的精度和實(shí)時(shí)性要求高,而且這些數(shù)據(jù)的處理具有高的乘法運(yùn)算密集性和加法運(yùn)算密集型,,使得數(shù)字信號(hào)處理器對(duì)乘加混合運(yùn)算和并行運(yùn)算的處理能力需求變得日益重要。 本文依托“YHFT-Matrix DSP”的開(kāi)發(fā)與研制,旨在研究和設(shè)計(jì)面向SIMD DSP的高性能定點(diǎn)算術(shù)運(yùn)算部件,以滿(mǎn)足數(shù)字信號(hào)處理器對(duì)乘加混合運(yùn)算和并行運(yùn)算的處理能力。該部件集成了加減法、乘法、乘加、乘減、點(diǎn)積和復(fù)數(shù)等各種運(yùn)算,并使這些運(yùn)算支持并行處理。本文的主要工作和貢獻(xiàn)如下: (1)采用并行前綴加法器中的Kogge-Stone樹(shù)結(jié)構(gòu),由符號(hào)位控制和進(jìn)位控制的方法實(shí)現(xiàn)了SIMD加法器,并添加飽和處理功能。該加法器能完成8/16/32/40位SIMD加法/減法,包括有符號(hào)/無(wú)符號(hào)運(yùn)算,且能工作在飽和模式和非飽和模式。 (2)采用符號(hào)預(yù)處理和拼接的技術(shù)對(duì)兩個(gè)16×8乘法器組合實(shí)現(xiàn)了16位SIMD乘法器,其中的16×8乘法器采用基4Booth編碼、以5-2和4-2壓縮器為主的華萊士壓縮樹(shù)和并行前綴Kogge-Stone樹(shù)結(jié)構(gòu)作為最終加法器的方法實(shí)現(xiàn)。同時(shí)本文設(shè)計(jì)了32位SIMD乘法器,該乘法器能完成8/16/32×16/32位SIMD有符號(hào)/無(wú)符號(hào)乘法。 (3)根據(jù)Mibench算法、LTE協(xié)議、4G無(wú)線(xiàn)協(xié)議和H.264中的核心算法的指令需求分析結(jié)果,本文設(shè)計(jì)了4站流水結(jié)構(gòu)的高性能定點(diǎn)算術(shù)運(yùn)算部件。該部件能有效的完成高并行性的乘法密集性和加法密集性運(yùn)算。 本文所設(shè)計(jì)的算術(shù)運(yùn)算部件應(yīng)用在YHFT-Matrix DSP芯片中,目前該芯片已經(jīng)流片成功,SDK板測(cè)試表明本算術(shù)運(yùn)算部件能很好的滿(mǎn)足SIMD DSP所面向的乘法密集性和加法密集性的嵌入式計(jì)算需求。
[Abstract]:In the embedded computing fields such as video image processing, radar signal processing and wireless communication, because of the large amount of data processing and the high parallelism of data, the precision and real-time performance of data calculation are very high. Moreover, the processing of these data is highly multiplicative and additive intensive, which makes the processing ability of the digital signal processor (DSP) more and more important. Based on the development and research of "YHFT-Matrix DSP", this paper aims to study and design a high performance fixed-point arithmetic unit for SIMD DSP, so as to satisfy the digital signal processor's ability to deal with multiplication and addition mixed operations and parallel operations. It integrates addition, subtraction, multiplication, multiplication, multiplication, multiplication, dot product and complex number, and makes these operations support parallel processing. The main work and contributions of this paper are as follows: The Kogge-Stone tree structure of the parallel prefix adder is adopted. The SIMD adder is realized by symbol bit control and carry control, and the saturation processing function is added. The adder can perform 8 / 16 / 32 / 40 bit SIMD addition / subtraction, including signed / unsigned operations, and can work in saturation mode and unsaturated mode. The 16-bit SIMD multiplier is implemented by combining two 16 脳 8 multipliers with symbol preprocessing and splicing, in which 16 脳 8 multipliers are coded by base 4Booth. The method of using the Wallace compression tree and the parallel prefix Kogge-Stone tree structure as the final adders is presented, which is mainly composed of 5-2 and 4-2 compressors. At the same time, a 32-bit SIMD multiplier is designed, which can accomplish the signed / unsigned multiplication of SIMD in 8-16-32 脳 16 / 32 bit. 3) according to the result of instruction requirement analysis of the 4G wireless protocol and the core algorithm in H.264, a 4-station pipelined high performance fixed-point arithmetic unit is designed in this paper. This part can effectively perform multiplication and addition dense operations with high parallelism. The arithmetic operation unit designed in this paper is used in YHFT-Matrix DSP chip. The test of the chip has been successful in SDKboard. The result shows that the arithmetic operation unit can meet the demand of SIMD DSP for multiplicative and additive intensive embedded computing.
【學(xué)位授予單位】:國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2012
【分類(lèi)號(hào)】:TP332.2
【參考文獻(xiàn)】
相關(guān)期刊論文 前2條
1 孫Pr彥;蔣劍飛;毛志剛;;一種數(shù)字信號(hào)處理器中的高性能乘加器設(shè)計(jì)[J];微電子學(xué);2010年01期
2 劉學(xué)政;張盛兵;黃小平;;支持短向量的32位快速加法器設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2010年09期
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