本文選題：FPGA + 相變存儲(chǔ)器　； 參考：《山東大學(xué)》2013年碩士論文

【摘要】：相變存儲(chǔ)器(Phase Change Memory)簡(jiǎn)稱PCM,是一種新型的非易失性存儲(chǔ)器,其具有諸多優(yōu)秀性能,是未來計(jì)算機(jī)應(yīng)用中閃存的最佳替代品,具有不可估量的發(fā)展前景。PCM掉電不丟失數(shù)據(jù),存儲(chǔ)時(shí)間長(zhǎng),工作功耗低,而且相對(duì)于閃存,PCM在編程(寫數(shù)據(jù))前不需要進(jìn)行擦除操作,支持對(duì)每一個(gè)存儲(chǔ)單元的隨機(jī)讀寫,其讀寫速度也高于閃存,每個(gè)PCM存儲(chǔ)單元的可編程次數(shù)也遠(yuǎn)超過閃存。根據(jù)科學(xué)界估計(jì),未來PCM的讀寫速度和可編程次數(shù)將逐漸接近甚至超過DRAM存儲(chǔ)器。因此,電子行業(yè)對(duì)PCM的需求增長(zhǎng)迅速,固態(tài)硬盤、手機(jī)ROM等存儲(chǔ)設(shè)備開始逐漸使用PCM作為其存儲(chǔ)介質(zhì)。與閃存一樣,PCM在普及應(yīng)用的過程中不但需要制造工藝的提升和硬件設(shè)計(jì)的完善,還需要高效的軟件模塊進(jìn)行管理和控制。本文根據(jù)PCM的特性和實(shí)際需求,設(shè)計(jì)了PCM并行控制器,并在FPGA中以Verilog HDL語言編程實(shí)現(xiàn),最終應(yīng)用于國(guó)家863項(xiàng)目“面向大數(shù)據(jù)的先進(jìn)存儲(chǔ)結(jié)構(gòu)及關(guān)鍵技術(shù)”的子包“基于新型非易失性存儲(chǔ)器的。統(tǒng)一內(nèi)外存’系統(tǒng)結(jié)構(gòu)及其關(guān)鍵技術(shù)”項(xiàng)目的統(tǒng)一內(nèi)外存實(shí)現(xiàn)中。 首先,本文根據(jù)對(duì)PCM的屬性歸納和PCM與其他存儲(chǔ)器的比較結(jié)果,結(jié)合各種計(jì)算機(jī)系統(tǒng)對(duì)PCM的功能要求,分析了PCM并行控制器的系統(tǒng)功能性需求和非功能性需求,確定了本系統(tǒng)的主要功能目標(biāo)和解決的問題,即控制PCM并與用戶相連接,實(shí)現(xiàn)和優(yōu)化用戶與PCM之間的通信。本文以用例圖等輔助說明了系統(tǒng)的需求分析。 其次,本文在需求分析基礎(chǔ)上對(duì)PCM并行控制器進(jìn)行了系統(tǒng)架構(gòu)設(shè)計(jì)。本文根據(jù)系統(tǒng)的功能需求提出了系統(tǒng)設(shè)計(jì)目標(biāo)和原則,并據(jù)此分別對(duì)系統(tǒng)的技術(shù)架構(gòu)和功能架構(gòu)進(jìn)行了設(shè)計(jì)。主要設(shè)計(jì)了用戶接口模塊、頁表管理模塊、分頁機(jī)制模塊、損耗均衡模塊、錯(cuò)誤校驗(yàn)?zāi)K、壞頁管理模塊和PCM接口模塊等功能模塊,以達(dá)到將PCM接口轉(zhuǎn)換為用戶接口并控制PCM高效安全的存儲(chǔ)用戶數(shù)據(jù)的目標(biāo)。本文還結(jié)合系統(tǒng)流程圖等說明了PCM并行控制器的工作原理等。 再次,本文根據(jù)上述工作進(jìn)行了PCM并行控制器的系統(tǒng)詳細(xì)設(shè)計(jì),完成了系統(tǒng)建模,結(jié)合類圖等說明了本系統(tǒng)的靜態(tài)結(jié)構(gòu),介紹了各個(gè)功能模塊之間的關(guān)系和靜態(tài)建模,隨后結(jié)合系統(tǒng)狀態(tài)圖等描述本系統(tǒng)的動(dòng)態(tài)結(jié)構(gòu),從讀操作和寫操作兩方面分析了系統(tǒng)的運(yùn)行路線和各個(gè)模塊之間的動(dòng)態(tài)關(guān)系。本文還結(jié)合模塊狀態(tài)圖等說明了各個(gè)模塊的詳細(xì)設(shè)計(jì)和整個(gè)系統(tǒng)的具體工作流程。 最后,本文根據(jù)對(duì)PCM并行控制器的詳細(xì)設(shè)計(jì)簡(jiǎn)單說明了各個(gè)模塊的實(shí)現(xiàn),介紹了本系統(tǒng)的物理模型,詳細(xì)解釋了頁表管理模塊和損耗均衡模塊中的地址映射、區(qū)域外更新和頁間動(dòng)態(tài)替換等算法實(shí)現(xiàn),以及錯(cuò)誤校驗(yàn)?zāi)K中的ECC校驗(yàn)算法實(shí)現(xiàn),并描述了移植了本系統(tǒng)的PCM開發(fā)板。本文還介紹了PCM并行控制器的測(cè)試環(huán)境,對(duì)本系統(tǒng)進(jìn)行了測(cè)試和驗(yàn)證,并對(duì)測(cè)試結(jié)果進(jìn)行了分析。 本文結(jié)尾總結(jié)了PCM并行控制器的功能和實(shí)現(xiàn),以及目前各種計(jì)算機(jī)系統(tǒng)與本系統(tǒng)的兼容和匹配,并展望了PCM應(yīng)用的發(fā)展方向。 綜上所述,本文分析了計(jì)算機(jī)系統(tǒng)對(duì)存儲(chǔ)設(shè)備的需求和PCM的屬性,并在此基礎(chǔ)上設(shè)計(jì)和實(shí)現(xiàn)了PCM并行控制器。
[Abstract]:Phase Change Memory (Memory), short for PCM, is a new nonvolatile memory. It has many excellent performances and is the best substitute for flash memory in future computer applications. It has an immeasurable prospect of developing.PCM power loss without losing data, long storage time, low power consumption, and PCM programming (write number) relative to flash memory According to scientific circles, the reading and writing speed and programmable times of PCM will gradually approach or even exceed the DRAM memory. Therefore, the electronic industry is to PC. The demand for M is growing rapidly, and the storage devices such as solid state hard disk and mobile phone ROM are gradually using PCM as its storage medium. As with flash memory, PCM needs not only the improvement of manufacturing process and the perfect hardware design, but also the efficient software modules for management and control in the process of universal application. This article is based on the characteristics and actual requirements of PCM. The PCM parallel controller is designed and implemented in FPGA with Verilog HDL language. It is finally applied to the unified internal and external implementation of the sub package of the National 863 project "the advanced storage structure and key technology for large data", which is based on the new non-volatile memory.
First, based on the attribute induction of PCM and the comparison between PCM and other memory, and combining the functional requirements of various computer systems to PCM, this paper analyzes the functional requirements and non functional requirements of the PCM parallel controller, and determines the problem of the main function target of this system, that is, to control the PCM and to connect with the user. The communication between users and PCM is optimized. The requirement analysis of the system is illustrated by use case diagram.
Secondly, the system architecture of PCM parallel controller is designed on the basis of demand analysis. According to the functional requirements of the system, the objectives and principles of the system design are put forward. According to this, the technical architecture and functional framework of the system are designed respectively. The main design is the user interface module, page table management module and paging mechanism module. The loss balance module, error check module, bad page management module and PCM interface module are used to achieve the goal of converting PCM interface into user interface and controlling PCM efficient and secure storage of user data. This paper also illustrates the working principle of PCM parallel controller in combination with system flow chart.
Thirdly, according to the above work, the detailed design of the PCM parallel controller is carried out, the system modeling is completed, the static structure of the system is explained with the class diagram, the relationship and static modeling of various functional modules are introduced. Then the dynamic structure of the system is described with the state diagram of the system, from the read operation and the write operation two. The operation route of the system and the dynamic relationship between each module are analyzed. The detailed design of each module and the specific work flow of the whole system are illustrated in this paper.
Finally, according to the detailed design of the PCM parallel controller, the realization of each module is simply explained, the physical model of the system is introduced, the address mapping in the page management module and the loss balance module, the updating of the area and the dynamic replacement between the pages, and the ECC verification algorithm in the error checking module are explained in detail. At present, the PCM development board which has been transplanted in this system is described. The test environment of the PCM parallel controller is introduced in this paper, and the system is tested and verified, and the test results are analyzed.
At the end of this paper, the function and implementation of PCM parallel controller are summarized, as well as the compatibility and matching of various computer systems with this system at present, and the development direction of the PCM application is also prospected.
To sum up, this paper analyzes the requirements of computer system for storage devices and the properties of PCM, and designs and implements PCM parallel controller on this basis.

【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP311.52;TP333

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本文編號(hào)：1800235