本文選題：軟件無線電 + 可重構(gòu)��； 參考：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：本文以軟件無線電為背景,重點著眼于其可重構(gòu)特性。結(jié)合數(shù)字通信系統(tǒng)中常用的FFT算法和Viterbi譯碼算法,通過分析FFT算法和Viterbi譯碼算法的運算過程,找到兩個算法結(jié)構(gòu)上的相似之處,據(jù)此提出新的可重構(gòu)的蝶形計算單元。在可重構(gòu)蝶形計算單元的基礎(chǔ)之上,提出了可重構(gòu)的FFT和Viterbi協(xié)處理器。主要貢獻包括:1.針對傳統(tǒng)數(shù)字通信系統(tǒng)中FFT算法和Viterbi譯碼算法單獨實現(xiàn),硬件資源開銷過大,不能很好地滿足軟件無線電靈活性要求的情況,結(jié)合軟件無線電的可重構(gòu)需要,提出將FFT算法和Viterbi譯碼算法用一個可重構(gòu)的硬件結(jié)構(gòu)實現(xiàn),達到了節(jié)省硬件開銷,增強硬件靈活性的目的。2.通過分析FFT算法和Viterbi算法的運算過程,找到兩個算法運算過程中的共同點,并在此基礎(chǔ)之上實現(xiàn)了可重構(gòu)的蝶形計算單元。該可重構(gòu)蝶形計算單元所需硬件資源,相對于分立實現(xiàn)的FFT算法和Viterbi譯碼算法的蝶形計算單元要少三分之一左右。3.在可重構(gòu)的蝶形計算單元基礎(chǔ)之上,提出了可重構(gòu)的FFT和Viterbi協(xié)處理器。該處理器不但可以在FFT算法和Viterbi算法之間切換,而且在FFT算法的實現(xiàn)上也實現(xiàn)了4點到1024點之間的可變點數(shù)的計算,Viterbi譯碼算法在碼率、約束長度以及生成函數(shù)都是在一定范圍內(nèi)可配置的。
[Abstract]:This paper focuses on the reconfigurable characteristics of software radio. Combined with FFT algorithm and Viterbi decoding algorithm commonly used in digital communication system, by analyzing the operation process of FFT algorithm and Viterbi decoding algorithm, the similarities between the two algorithms are found, and a new reconfigurable butterfly computing unit is proposed. On the basis of reconfigurable butterfly computing unit, reconfigurable FFT and Viterbi coprocessors are proposed. The main contributions include: 1. In the traditional digital communication system, the FFT algorithm and the Viterbi decoding algorithm are implemented separately, and the hardware resources are too expensive to meet the flexible requirements of software radio. The reconfigurable requirements of software radio are combined. The FFT algorithm and the Viterbi decoding algorithm are implemented with a reconfigurable hardware structure, which can save the hardware cost and enhance the flexibility of the hardware. By analyzing the operation process of FFT algorithm and Viterbi algorithm, the common points of the two algorithms are found, and the reconfigurable butterfly computing unit is realized on this basis. The hardware resource of the reconfigurable butterfly computing unit is about 1/3 less than that of the discrete FFT algorithm and the Viterbi decoding algorithm. Reconfigurable FFT and Viterbi coprocessors are proposed on the basis of reconfigurable butterfly computing units. The processor can not only switch between FFT algorithm and Viterbi algorithm, but also realize the calculation of variable points from 4 points to 1024 points in the implementation of FFT algorithm. The constraint length and the generating function are configurable in a certain range.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TN92

【參考文獻】

相關(guān)碩士學(xué)位論文 前1條

1 李日亮;基于DSP的軟件無線電平臺的研究與實現(xiàn)[D];西安電子科技大學(xué);2011年

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本文編號：1799822