本文選題：片上多處理器 + 雙模式融合通信��； 參考：《東北大學》2013年博士論文

【摘要】：傳統(tǒng)單核處理器受到功耗及制造工藝的限制,已無法通過提升主頻來滿足高性能嵌入式應用的需求。因此,學者們提出了片上多處理器系統(tǒng)的研究方向。與多處理器系統(tǒng)相比,片上多處理器系統(tǒng)將處理單元集成在單顆芯片中,減少了通信代價,降低了功耗,進一步提升了系統(tǒng)的整體性能。因此,片上多處理器系統(tǒng)是未來計算機發(fā)展的方向和必然趨勢。隨著研究的不斷深入,越來越多的應用被映射到片上多處理器系統(tǒng)中,然而此過程所遇到的一些問題沖擊了現(xiàn)有的系統(tǒng)架構,此類問題的核心是如何保證和提高系統(tǒng)的并行效率。為此,本文從通信機制、設計模型、路由算法、拓撲結構等關鍵領域,展開了深入的研究,并取得了如下創(chuàng)新性成果：(1)提出了一種雙模式融合的通信機制。處理器間的通信機制是影響片上多處理器系統(tǒng)性能的關鍵因素,針對已有通信機制存在通信效率低的問題,提出了一種雙模式融合通信機制。該機制根據(jù)處理器間交互數(shù)據(jù)的特征,將其劃分為控制類消息和數(shù)據(jù)類消息,分別采用獨立的通道完成傳輸�；陔p模式融合通信機制,提出了復制-分治的任務并行化模型,通過預先對任務復制,減少運行時處理器問的調度開銷。基于可重構平臺,對雙模式融合通信機制進行了實現(xiàn),并以粒子濾波跟蹤算法為例,進行了任務并行化設計。測試結果表明,雙模式融合通信機制能夠顯著提升處理器間的數(shù)據(jù)交互能力,降低并行開銷,提高系統(tǒng)整體的并行效率。(2)提出了一種多層次并行的設計模型。根據(jù)應用需求設計合理的系統(tǒng)架構及任務調度方式,是提高異構片上多處理器系統(tǒng)性能的關鍵。已有的設計模型雖然可以提高系統(tǒng)的并行性,但仍然沒有擺脫宏觀串行、局部并行的模式。針對以上問題,提出了一種多層次并行的設計模型。將異構系統(tǒng)的設計分解為系統(tǒng)級、事務級和語句級三個層次,通過逐層深入、逐步分解的方式挖掘任務的并行性,提高系統(tǒng)整體性能。以多層次并行模型為基礎,基于可重構平臺,設計并實現(xiàn)了AVI視頻編碼及存儲系統(tǒng)。測試結果表明,多層次并行模型有效的解決了異構片上多處理器系統(tǒng)的設計問題,提高了系統(tǒng)并行效率。(3)提出了一種基于阻塞感知的局部自適應路由算法。已有路由算法對拓撲網絡利用率低,數(shù)據(jù)包路由過程容易產生局部阻塞,針對此問題,提出了一種基于阻塞感知的局部白適應路由算法。該路由算法采取全局維序、局部自適應的規(guī)則,在路由節(jié)點間增加阻塞反饋信號,對鄰近區(qū)域的網絡狀態(tài)進行監(jiān)控,并能夠根據(jù)實際情況動態(tài)調整路由路徑。理論分析及仿真結果表明：該算法具有較高的數(shù)據(jù)吞吐率和較強的自適應能力。基于可重構平臺,對本文提出的算法和XY路由算法進行了實現(xiàn)。對比測試表明,采用本文所提出的算法進行路由時,有多條最短路徑可以選擇,降低了單一鏈路的負載。同時,當網絡出現(xiàn)阻塞時,可有效的繞過阻塞區(qū)域,提高系統(tǒng)的并行性。(4)提出了一種基于折半思想的拓撲結構。NoC型片上多處理器系統(tǒng)中,主節(jié)點與其它節(jié)點的數(shù)據(jù)交互頻率要遠高于普通節(jié)點間的交互頻率,而目前的拓撲結構研究并沒有面向這一特征進行優(yōu)化設計。針對此問題,提出一種新型的拓撲結構Half-Mesh。該拓撲通過增加行、列頭節(jié)點與普通節(jié)點間橫向、縱向長連線,縮短了頭節(jié)點與同維的中心節(jié)點間距離,繼而減小了整個NoC網絡的平均路徑長度。針對Half-Mesh拓撲結構,提出了HTF-XY路由算法,采取分區(qū)路由策略,既縮短了不同區(qū)域內節(jié)點間的路徑長度,又提升路由的自適應性�；诳芍貥嬈脚_,實現(xiàn)了網絡規(guī)模為7×7的Half-Mesh拓撲結構及HTF-XY路由算法。測試結果表明,Half-Mesh拓撲結構提升了頭節(jié)點與其它節(jié)點的交互能力,降低了整個片上網絡的路由延遲,提高系統(tǒng)的并行性。
[Abstract]:The traditional mononuclear processor is limited by power and manufacturing technology. It has not been able to meet the needs of high performance embedded applications by lifting the main frequency. Therefore, scholars have proposed the research direction of the on-chip multiprocessor system. Compared with the multiprocessor system, the chip multiprocessor system integrates processing units in single chips and reduces the pass. It reduces power consumption and further improves the overall performance of the system. Therefore, the on-chip multiprocessor system is the direction and inevitable trend of future computer development. As the research continues, more and more applications are mapped to on chip multiprocessor systems. However, some of the problems encountered in this process have impacted the existing systems. The core of such problems is how to ensure and improve the parallel efficiency of the system. Therefore, this paper has carried out an in-depth study on the key fields such as communication mechanism, design model, routing algorithm, topology structure and other key fields, and obtained the following innovative achievements: (1) a communication mechanism of dual mode fusion is proposed. The communication mechanism among processors is the mechanism of communication between the processors. The key factor affecting the performance of the multiprocessor system on the chip is a dual mode fusion communication mechanism, which is based on the characteristics of the interactive data between processors. This mechanism divides it into a control class message and a data class message according to the characteristics of the interactive data between the processors. A task parallelization model of duplication and division is proposed in the mode fusion mechanism. By copying the tasks in advance, the scheduling overhead of the processor is reduced. Based on the reconfigurable platform, the dual mode fusion communication mechanism is implemented. The task parallelization design is carried out with the particle filter tracking algorithm. The test results show that The dual mode fusion communication mechanism can significantly improve the data interaction capability between processors, reduce the parallel overhead and improve the overall parallel efficiency of the system. (2) a multi level parallel design model is proposed. The design of a reasonable system architecture and task scheduling method based on the application requirements is the key to improving the performance of the heterogeneous multiprocessor system. Key. Although the existing design model can improve the parallelism of the system, it still does not get rid of the macro serial and local parallel mode. In view of the above problems, a multi level parallel design model is proposed. The design of the heterogeneous system is decomposed into three levels of system level, transaction level and statement level, which are gradually decomposed by layer by layer. Based on the multilevel parallel model and the reconfigurable platform, the AVI video coding and storage system is designed and implemented on the basis of the multilevel parallel model. The test results show that the multilevel parallel model effectively solves the design problem of the multiprocessor system on the heterogeneous chip and improves the efficiency of the system parallel. (3) proposed A local adaptive routing algorithm based on blocking perception is proposed. The existing routing algorithm has a low utilization rate to the topology network and easily produces local congestion in the packet routing process. A local white adaptive routing algorithm based on blocking perception is proposed for this problem. The routing algorithm takes the global order, local adaptive rules and routing. The congestion feedback signal is added between nodes to monitor the network state in the adjacent area, and the routing path can be dynamically adjusted according to the actual situation. The theoretical analysis and simulation results show that the algorithm has high data throughput and strong adaptive ability. Based on reconfigurable platform, the algorithm proposed in this paper and the XY routing algorithm are introduced. The comparison test shows that when the algorithm proposed in this paper is used for routing, there are several shortest paths that can be selected to reduce the load of a single link. At the same time, when the network is blocked, it can effectively bypass the blocking area and improve the parallelism of the system. (4) a topology structure.NoC type based on the half thought is proposed. In the processor system, the frequency of the data interaction between the main node and the other nodes is much higher than the interaction frequency between the common nodes, and the current topology research has not been optimized for this feature. A new topology, Half-Mesh., is proposed. Transverse and lengthwise long lines shorten the distance between the head node and the center node of the same dimension, and then reduce the average path length of the whole NoC network. In view of the Half-Mesh topology, the HTF-XY routing algorithm is proposed and the partition routing strategy is adopted, which not only shortens the path length among the nodes in different regions, but also improves the adaptability of the routing. The reconfigurable platform has realized the network size of 7 * 7 Half-Mesh topology and HTF-XY routing algorithm. The test results show that the Half-Mesh topology improves the interaction between the head node and other nodes, reduces the routing delay of the entire network and improves the parallelism of the system.

【學位授予單位】：東北大學
【學位級別】：博士
【學位授予年份】：2013
【分類號】：TP332

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本文編號：1792270