本文選題：專用指令集處理器 + 互連網(wǎng)絡(luò)��； 參考：《西安電子科技大學(xué)》2012年碩士論文

【摘要】：在數(shù)字信號(hào)處理的應(yīng)用中，通常采用數(shù)字信號(hào)處理器(DSP)或者專用集成電路(ASIC)來實(shí)現(xiàn)，但是它們都難以同時(shí)達(dá)到高速處理，，低功耗和靈活應(yīng)用等要求。而專用指令集處理器(ASIP)既有ASIC的高速性，又包含DSP可編程的特點(diǎn)，能有效權(quán)衡兩者性能，特別適合在FPGA內(nèi)以大規(guī)模并行處理的方式來實(shí)現(xiàn)復(fù)雜的應(yīng)用。本文依托實(shí)驗(yàn)室項(xiàng)目，針對(duì)ASIP并行體系結(jié)構(gòu)和功能單元（FU）的設(shè)計(jì)及應(yīng)用，主要進(jìn)行了以下四方面工作： 第一，針對(duì)ASIP并行處理機(jī)中各個(gè)處理單元之間數(shù)據(jù)交換的問題，設(shè)計(jì)了一種基于多端口共享存儲(chǔ)器互連網(wǎng)絡(luò)的緊耦合結(jié)構(gòu)。然后，在此結(jié)構(gòu)上實(shí)現(xiàn)了1024點(diǎn)FFT算法，驗(yàn)證了這種結(jié)構(gòu)設(shè)計(jì)的正確性。 第二，針對(duì)FFT算法在匯編編程中存在頻繁使用同一基本運(yùn)算的問題，設(shè)計(jì)了一種專用蝶形運(yùn)算單元，從而有效減少了指令數(shù)目，縮短了執(zhí)行時(shí)間，提高了處理速度。 第三，針對(duì)微波壓縮感知成像算法工程化實(shí)現(xiàn)這個(gè)項(xiàng)目，提出了一種采用ASIP并行處理結(jié)構(gòu)來實(shí)現(xiàn)的解決方案。然后，針對(duì)算法在ASIP并行處理機(jī)上的可行性進(jìn)行了研究，得出了一些在ASIP上實(shí)現(xiàn)所需要的設(shè)計(jì)要素。 第四，針對(duì)H.264壓縮項(xiàng)目中二進(jìn)制算術(shù)編碼算法硬件的實(shí)現(xiàn)提出了一種采用ASIP功能單元嵌入式處理實(shí)現(xiàn)的方法。首先，基于ASIP可參量化設(shè)計(jì)平臺(tái)設(shè)計(jì)了一款24位ASIP，并在此ASIP上實(shí)現(xiàn)了二進(jìn)制算術(shù)編碼。然后，針對(duì)二進(jìn)制算法的特點(diǎn)，對(duì)ASIP指令集進(jìn)行了改進(jìn)，設(shè)計(jì)了一種基于桶形移位器的可變長(zhǎng)度的移位指令以及實(shí)現(xiàn)電路。
[Abstract]:In the application of digital signal processing (DSP) or ASIC, it is difficult to meet the requirements of high speed processing, low power consumption and flexible application at the same time. Special instruction set processor (ASIP) not only has the high speed of ASIC, but also has the programmable characteristics of DSP, so it can effectively balance the performance of both. It is especially suitable for realizing complex applications in FPGA by large-scale parallel processing. This paper, based on the laboratory project, aims at the design and application of ASIP parallel architecture and function unit (FU), mainly carries on the following four aspects of work: Firstly, aiming at the problem of data exchange among processing units in ASIP parallel processor, a tight coupling structure based on multi-port shared memory interconnection network is designed. Then, the 1024 point FFT algorithm is implemented on this structure, which verifies the correctness of the structure design. Secondly, aiming at the problem that FFT algorithm frequently uses the same basic operation in assembly programming, a special butterfly operation unit is designed, which effectively reduces the number of instructions, shortens the execution time and improves the processing speed. Thirdly, aiming at the engineering implementation of microwave compression sensing imaging algorithm, a solution using ASIP parallel processing architecture is proposed. Then, the feasibility of the algorithm in ASIP parallel processing machine is studied, and some design elements for ASIP implementation are obtained. Fourthly, a method of embedded processing based on ASIP function unit is proposed for the hardware implementation of binary arithmetic coding algorithm in H.264 compression project. Firstly, a 24 bit ASIP is designed based on ASIP parameterized design platform, and binary arithmetic coding is implemented on this ASIP. Then, according to the characteristics of binary algorithm, the ASIP instruction set is improved, and a variable length shift instruction based on bucket shifter is designed and implemented.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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