本文選題：ADL + LISA��； 參考：《國防科學技術大學》2013年碩士論文

【摘要】：處理器建模在設計空間探索、軟硬件協(xié)同驗證、專用處理器設計等領域有著重要的作用。體系結構設計者需要對處理器多種體系結構進行評估，尋找目標需求和實現(xiàn)代價之間最佳平衡點，方便迅速地描述處理器體系結構模型是必經的途徑；軟件人員需要盡早地開發(fā)和調試配套軟件，功能正確且完備的硬件模型是開發(fā)環(huán)境不可或缺的部分；驗證人員需要從功能和性能等多個方面評價模型可用性與可實現(xiàn)性，靈活可修改的模型與基礎工具鏈是必備的條件。因此，研究處理器的快速建模生成方法具有十分重要的意義。 某款高性能CPU經過多代發(fā)展已經積累了大量體系結構設計方案可供選擇，出于未來高性能微處理器設計驗證進度的考慮，使用快速驗證原型能夠在原型精確度與早期軟件開發(fā)需求之間取得平衡。本課題針對該項目快速產生處理器模型和軟件工具的需求展開研究與設計，以RISC-P體系結構模擬新處理器結構，課題的主要工作和研究成果包括以下幾個方面： 1)課題綜合參考多種RISC指令集的基礎上自定義RISC-P指令集；指令類型涵蓋數(shù)據(jù)處理類指令、分支指令、乘加類指令、訪存類指令。然后，基于自定義指令集設計了64位RISC-P架構的微體系結構。 2)使用LISA語言描述了指令集精確和周期精確兩種抽象級別的處理器模型。使用Processor Designer工具，基于周期精確的仿真模型，得到自定義指令的軟件工具鏈、處理器RTL源碼以及指令描述文檔。然后，本課題使用DC工具在45nm工藝庫下對RTL代碼進行綜合，模型運行頻率為334MHz，功耗為25.9174681mW，面積為0.5894mm2。 3)遵循冗余驗證的原則，本課題實現(xiàn)了基于PD平臺的微處理器模型仿真與調試，基于生成的RTL代碼軟模擬邏輯驗證和硬件加速器驗證。兩種途徑均分為單條指令的測試和針對性測試程序測試兩個步驟進行。多種方式結果證明基于快速原型方法的處理器模型能夠取得模擬精度與架構調整靈活性的折中。 4)以片上存儲器容量設計調整和增加分支預測部件為例，驗證了快速原型方法能夠靈活支持DSE。結合綜合工具與廠商工藝庫能夠快速評估設計調整帶來的面積、主頻和功耗影響，同時體系結構模擬工具能夠用于軟件開發(fā)和特定軟件應用性能評估。 基于自定義處理器體系結構資料，，課題以Processor Designer工具為基礎探索了快速原型方法在微處理器設計與驗證過程中的應用。試驗過程與結果表明該方法能夠支持快速設計建模、體系結構參數(shù)空間探索、軟件應用功能驗證和開發(fā)、以及物理設計性能評估。
[Abstract]:Processor modeling plays an important role in the field of design space exploration, hardware and software co-verification, dedicated processor design and so on.Architecture designers need to evaluate the processor architecture to find the best balance between the target requirements and the implementation cost, and describe the processor architecture model conveniently and quickly.Software personnel need to develop and debug the supporting software as soon as possible. A proper and complete hardware model is an indispensable part of the development environment, and verifiers need to evaluate the usability and realizability of the model from many aspects, such as function and performance, etc.Flexible modifiable models and basic tool chains are required.Therefore, it is of great significance to study the fast modeling generation method of processor.A certain high-performance CPU has accumulated a large number of architecture design schemes to choose from after many generations of development, considering the design verification progress of future high-performance microprocessors.Using rapid prototyping can strike a balance between prototype accuracy and early software development requirements.This topic aims at the requirement of the project to produce the processor model and software tools quickly, and simulates the new processor architecture with the RISC-P architecture. The main work and research results include the following aspects:The main contents are as follows: 1) the subject synthetically refers to various RISC instruction sets and customizes the RISC-P instruction set. The instruction type includes data processing instruction, branch instruction, multiplicative and additive instruction, memory access instruction.Then, a 64-bit RISC-P architecture is designed based on custom instruction set.2) the processor model of instruction set precision and periodic precision is described by using LISA language.Using the Processor Designer tool, the software tool chain, the processor RTL source code and the instruction description document are obtained based on the cycle precise simulation model.Then, the DC tool is used to synthesize the RTL code in the 45nm process library. The running frequency of the model is 334MHz, the power consumption is 25.9174681mW, and the area is 0.5894mm2.3) following the principle of redundancy verification, this paper realizes the simulation and debugging of microprocessor model based on PD platform, the software simulation logic verification based on generated RTL code and the verification of hardware accelerator.The two approaches are divided into two steps: single instruction test and targeted test program test.The results show that the processor model based on rapid prototyping method can achieve a compromise between simulation accuracy and flexibility of architecture adjustment.4) taking the design and adjustment of on-chip memory capacity and the addition of branch prediction components as examples, it is verified that the rapid prototyping method can support DSEs flexibly.The combination of integrated tools and vendor process libraries can quickly evaluate the impact of design adjustment on area, main frequency and power consumption, while architecture simulation tools can be used for software development and performance evaluation of specific software applications.Based on the data of custom processor architecture, this paper explores the application of rapid prototyping method in microprocessor design and verification based on Processor Designer tools.The experimental process and results show that this method can support rapid design modeling, architecture parameter space exploration, software application function verification and development, and physical design performance evaluation.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332

【參考文獻】

相關期刊論文 前2條

1 Dhanendra Jani;Steve Leibson;;Tensilica如何驗證處理器核心[J];中國集成電路;2008年09期

2 嚴迎建;葉建森;劉軍偉;徐勁松;;VLIW處理器ISA建模與輔助軟件優(yōu)化技術[J];計算機工程與設計;2009年11期

本文編號：1771655