本文選題：固態(tài)盤 + 多通道��； 參考：《華中科技大學(xué)》2012年碩士論文

【摘要】：傳統(tǒng)硬盤因內(nèi)部存在機(jī)械運行部件，導(dǎo)致其速度慢，功率大且抗震性差。固態(tài)盤(Solid State Disk，SSD)以閃存作為存儲介質(zhì)，擁有高性能、低功耗和低噪聲等諸多優(yōu)點，在很多應(yīng)用領(lǐng)域中，是傳統(tǒng)硬盤的理想替代品。Flash的固有讀寫延遲，導(dǎo)致單片F(xiàn)lash讀寫速度不高，接口帶寬受限。由于MLC(Multi-Level Cell) Flash的出現(xiàn)，這個問題變得越來越嚴(yán)重。隨著Flash應(yīng)用技術(shù)的不斷改進(jìn)，用戶對設(shè)備的讀寫速度要求也逐漸提高，單顆�；蛘邌瓮ǖ赖拈W存設(shè)備的接口帶寬已經(jīng)遠(yuǎn)遠(yuǎn)不能滿足用戶的要求。 為了解決閃存芯片接口的讀寫帶寬瓶頸，采用了固態(tài)存儲設(shè)備的多通道的設(shè)計。多通道閃存設(shè)備的優(yōu)點在于多通道能并行操作，成倍地提高固態(tài)存儲設(shè)備的讀寫帶寬。 在分析多通道固態(tài)盤的硬件架構(gòu)的基礎(chǔ)上，提出相應(yīng)的管理層體系架構(gòu)，完成了該固態(tài)盤存儲系統(tǒng)的設(shè)計與實現(xiàn)：包括系統(tǒng)區(qū)與數(shù)據(jù)區(qū)的劃分，隊列管理、緩沖區(qū)管理、并行存儲管理和閃存轉(zhuǎn)換層。 該系統(tǒng)通過多通道的并行和通道間的流水，實現(xiàn)了數(shù)據(jù)的并行傳輸，有效的提高了固態(tài)盤讀寫速度和系統(tǒng)容量。并且，為了與目前主流接口無縫銜接，采用了隊列管理，分離了讀寫隊列，設(shè)計了執(zhí)行隊列和完成隊列。該系統(tǒng)設(shè)計中包括數(shù)據(jù)緩沖策略，減少熱數(shù)據(jù)對Flash的寫操作，提高了讀寫性能以及Flash的壽命。此外，該系統(tǒng)設(shè)置了Flash轉(zhuǎn)換層，完成地址映射，垃圾回收等。Flash轉(zhuǎn)換層的地址映射采用高效的頁映射方式，，由于頁映射方式對于SDRAM的消耗較大，又提出了根據(jù)負(fù)載部分調(diào)入映射表的映射方式以及兩級頁映射的映射方法，這兩種方法都有效的減少了映射表對SDRAM的消耗。 由于Flash控制器是基于Altera公司的EP2C35F484C6N FPGA實現(xiàn)的，其屬于中低端的FPGA，且系統(tǒng)無操作系統(tǒng)支持。所以，F(xiàn)TL層的測試性能只有Flash控制器端的不足40%。在多通道的架構(gòu)及管理下，讀寫性能比較單顆粒的方式均有所加倍。
[Abstract]:The traditional hard disk has low speed, high power and poor seismic resistance because of the mechanical components inside.Solid State disk SSDs use flash memory as storage medium, which has many advantages, such as high performance, low power consumption and low noise. In many applications, it is the ideal substitute for traditional hard disk. Flash is the ideal substitute for the inherent read-write delay, which leads to the low read-write speed of monolithic Flash.The interface bandwidth is limited.With the emergence of MLC(Multi-Level Cell Flash, the problem becomes more and more serious.With the continuous improvement of Flash application technology, users' requirements for the speed of reading and writing of devices are also gradually increased. The interface bandwidth of single particle or single channel flash memory devices is far from being able to meet the requirements of users.In order to solve the bottleneck of read and write bandwidth of flash memory interface, a multi-channel design of solid state storage device is adopted.The advantage of multi-channel flash memory is that multi-channel can operate in parallel and increase the read and write bandwidth of solid-state storage device.On the basis of analyzing the hardware architecture of multi-channel solid-state disk, the corresponding management system architecture is put forward, and the design and implementation of the solid-state disk storage system are completed, including the partition of system area and data area, queue management, buffer management, etc.Parallel storage management and flash conversion layer.The system realizes the parallel transmission of data through the parallel of multi-channel and income between channels, and effectively improves the speed of reading and writing of solid-state disk and the capacity of the system.Moreover, in order to connect seamlessly with the current mainstream interface, queue management is adopted, read and write queues are separated, execution queues and completion queues are designed.Data buffering strategy is included in the design of the system, which reduces the write operation of hot data to Flash, and improves the performance of reading and writing and the lifetime of Flash.In addition, the system sets up the Flash translation layer, completes the address mapping, garbage collection and so on. The address mapping of .Flash translation layer adopts the efficient page mapping method, because the page mapping method consumes more to the SDRAM,The mapping method based on load part call mapping table and two-level page mapping is proposed. Both of these two methods can effectively reduce the consumption of mapping table to SDRAM.Because the Flash controller is based on the EP2C35F484C6N FPGA of Altera, it belongs to the middle and low end FPGA, and the system has no operating system support.So the test performance of FTL layer is only 40% less than that of Flash controller.Under multi-channel architecture and management, the performance of read and write is doubled compared with single particle.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333

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