本文選題：USB1.1　切入點(diǎn)：驗(yàn)證　出處：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：USB技術(shù)現(xiàn)已被廣泛應(yīng)用。本文綜合了對SOC設(shè)計(jì)的理解和對USB接口通信協(xié)議的分析，給出USB1.1控制器的設(shè)計(jì)方案，具有較高的實(shí)用價(jià)值。該芯片已經(jīng)應(yīng)用于加密U-Key并向各公司提供使用。 本文從SOC安全芯片的意義出發(fā)，以設(shè)計(jì)USB1.1設(shè)備控制器為目標(biāo)，分別對設(shè)計(jì)中出現(xiàn)的問題給出解決方案。通過對采樣得到的信號同步化，并根據(jù)相位檢測及沿檢測兩個(gè)信號得到接收數(shù)據(jù)時(shí)所用時(shí)鐘，實(shí)現(xiàn)接收時(shí)鐘的萃取。參考USB2.0給出的UTMI信號流程，用狀態(tài)機(jī)實(shí)現(xiàn)對包及標(biāo)識符的解碼、標(biāo)志信號生成和發(fā)送，并檢測總線上信號，實(shí)現(xiàn)對當(dāng)前端點(diǎn)是否空閑或Halt等的判定，以確認(rèn)USB系統(tǒng)是否進(jìn)入低功耗模式。在整個(gè)設(shè)計(jì)對RAM的連接關(guān)系上，主要是考慮USB重發(fā)機(jī)制的影響，，需使當(dāng)前地址暫存一個(gè)周期，在對數(shù)據(jù)進(jìn)行確認(rèn)之后才更新當(dāng)前地址，確保數(shù)據(jù)接收及發(fā)送地址無誤。并通過搭建驗(yàn)證平臺對USB進(jìn)行系統(tǒng)仿真，來保證設(shè)計(jì)的正確性，結(jié)合CV測試來確認(rèn)設(shè)計(jì)的完備性。 驗(yàn)證結(jié)果表明，本文給出的USB1.1設(shè)備控制器設(shè)計(jì)能夠正常解析USB1.1所支持的USB包，通過0端完成設(shè)備的枚舉及各端點(diǎn)的地址分配，并能正常進(jìn)行Bulk、Control、Interrupt傳輸。此外，除去文中MLBI模塊，剩余模塊所完成的功能及預(yù)留出的接口可以正常的完成其作為USB1.1設(shè)備控制器IP的應(yīng)用，能夠集成到SOC系統(tǒng)當(dāng)中。
[Abstract]:USB technology has been widely applied now. This paper synthesizes the understanding of SOC design and the analysis of USB interface communication protocol, and gives the design scheme of USB1.1 controller, which has high practical value. The chip has been applied in encrypting U-Key and provides it to all companies.
This article from the meaning of the SOC security chip, the design of USB1.1 device controller as the goal, are the problems in the design are given solutions. Through the synchronization of signal sampling, and according to the data obtained by the receiving clock phase detection and edge detection of two signals, realize the extraction of the receive clock UTMI signal. Process reference given by USB2.0, and the decoding of packet identifier using state machine, signal generation and transmission, and detection of the bus signal, determine whether the current endpoint of idle or Halt, to confirm whether the USB system into a low power mode. In the connection between the whole design of RAM, mainly considering the effect of the USB retransmission mechanism, the current need to address temporary one cycle, to update the current address in the data are confirmed, ensure the data receiving and sending address is correct. And through the build verification level The platform makes a systematic simulation of the USB to ensure the correctness of the design and to confirm the completeness of the design with the CV test.
The verification results show that the design of USB1.1 device controller is presented in this paper can support the normal analytical USB1.1 USB package, address distribution equipment and the enumeration is accomplished by 0 end points, and the normal Bulk, Control, Interrupt transmission. In addition, the removal of the MLBI module, the remaining module completed function and interface is reserved the normal completion of its application as a USB1.1 device controller IP, can be integrated into the SOC system.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP334.7

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本文編號：1720563