本文選題：片上多核處理器　切入點(diǎn)：功耗評估　出處：《湖南大學(xué)》2013年碩士論文

【摘要】：功耗評估是功耗優(yōu)化的基礎(chǔ)。近年來，功耗已經(jīng)成為處理器設(shè)計(jì)的重要限制因素，更凸顯了功耗評估在處理器設(shè)計(jì)中的作用。單核處理器時(shí)代已經(jīng)過去，片上多核處理器不可阻擋地成為當(dāng)今處理器的主流。如何為片上多核處理器建立準(zhǔn)確的功耗模型成為學(xué)術(shù)界研究的熱點(diǎn)課題之一。 根據(jù)芯片設(shè)計(jì)的不同階段，功耗評估方法分為結(jié)構(gòu)級、寄存器傳輸級、門級、晶體管級四種類型，其中結(jié)構(gòu)級和門級功耗評估方法由于各自鮮明的特點(diǎn)，獲得了最多的關(guān)注。然而，，隨著處理器設(shè)計(jì)方法的轉(zhuǎn)變和制造工藝的進(jìn)步，使得原有的結(jié)構(gòu)級功耗評估方法已經(jīng)無法準(zhǔn)確地估算處理器的功耗；而門級功耗評估方法由于需要具體的電路信息，不能在設(shè)計(jì)初期對處理器的功耗做出及時(shí)的評估和反饋。針對上述不足，本文提出了一種結(jié)合結(jié)構(gòu)級和門級的功耗評估方法。該方法既繼承了結(jié)構(gòu)級功耗評估方法的速度，又能改善其精度，同時(shí)，還具有一定的靈活性。具體研究工作如下： 首先，分別在電路級和體系結(jié)構(gòu)級劃分多核處理器。電路級劃分的依據(jù)是處理器功能電路體現(xiàn)出來的不同功耗特點(diǎn)，電路類型劃分為：組合邏輯，時(shí)序邏輯和互連線，為每種類型選用合適的功耗建模方法，即門級功耗分析方法或者結(jié)構(gòu)級功耗分析方法；體系結(jié)構(gòu)級劃分的依據(jù)是模塊的功能，將處理器核心，片上網(wǎng)絡(luò)，片上高速緩存和時(shí)鐘網(wǎng)絡(luò)劃分為模塊的組合，并將這些模塊映射到上述電路類型中的一種。 然后，對于適合用門級功耗分析方法測算功耗的基本模塊，依照集成電路的設(shè)計(jì)流程，從RTL代碼的設(shè)計(jì)開始，經(jīng)過綜合、布局、布線等一系列流程，得到門級網(wǎng)表，由門級網(wǎng)表分析得到基本模塊的門級功耗值。RTL代碼的設(shè)計(jì)考慮了基本模塊的體系結(jié)構(gòu)參數(shù)和結(jié)構(gòu)設(shè)計(jì)，盡可能地涵蓋基本模塊所能出現(xiàn)的各種情況，并將這些功耗值制成功耗查找表的形式。 最后，修改結(jié)構(gòu)級功耗模擬器McPAT，使本文中的功耗查找表集成其中；配置Gem5使其模擬目標(biāo)處理器的運(yùn)行；修改性能模擬器Gem5，使其能記錄程序運(yùn)行時(shí)各模塊的訪問次數(shù)。 實(shí)驗(yàn)結(jié)果表明，與結(jié)構(gòu)級功耗評估工具M(jìn)cPAT相比，本文的功耗評估方法可以更準(zhǔn)確地評估功耗。
[Abstract]:Power evaluation is the basis of power optimization.In recent years, power consumption has become an important limiting factor in processor design, which highlights the role of power evaluation in processor design.The era of single-core processors has passed and multi-core processors on-chip have become the mainstream of processors.How to build an accurate power model for multi-core processors on-chip has become one of the hot topics in academic research.According to the different stages of chip design, power evaluation methods are divided into four types: structure level, register transfer level, gate level and transistor level.However, with the change of processor design method and the progress of manufacturing technology, it is impossible to estimate the power consumption of the processor in the original structure level power evaluation method, and the gate level power evaluation method requires specific circuit information.The power consumption of the processor can not be evaluated and feedback in time at the beginning of the design.In order to solve these problems, this paper proposes a power evaluation method combining structure level and gate level.This method not only inherits the speed of the structure level power evaluation method, but also improves its accuracy. At the same time, it has some flexibility.The specific studies are as follows:First, multi-core processors are divided at circuit level and architecture level, respectively.The circuit level partition is based on the different power consumption characteristics of the processor functional circuit. The circuit types are divided into combinational logic, sequential logic and interconnect lines, and a suitable power modeling method is selected for each type.That is, gate power analysis method or structure-level power analysis method, architecture level partition is based on the function of the module, the processor core, on-chip network, on-chip cache and clock network are divided into modules.These modules are mapped to one of the above circuit types.Then, for the basic module which is suitable for power analysis at gate level, according to the design flow of integrated circuit, starting with the design of RTL code, after a series of processes such as synthesis, layout, wiring and so on, the gate level network table is obtained.The gate power consumption value. RTL code of the basic module is obtained by analyzing the gate network table. The architecture parameters and structure design of the basic module are considered, and the various situations that can occur in the basic module are covered as much as possible.These power values are made into a power look-up table.Finally, the structure level power simulator McPATs are modified to integrate the power look-up table in this paper; the Gem5 is configured to simulate the operation of the target processor; and the performance simulator, Gem5, is modified to record the number of visits to each module while the program is running.The experimental results show that the proposed method is more accurate than the structure level power evaluation tool McPAT.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332

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相關(guān)期刊論文 前2條

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本文編號：1707723