本文選題：存儲器　切入點：云架構(gòu)　出處：《太原理工大學(xué)》2015年碩士論文

【摘要】：存儲器作為一種信息存儲部件，是所有電子計算機(jī)系統(tǒng)的重要組成部分，其性能直接影響整個電子計算機(jī)系統(tǒng)性能。一直以來存儲容量和訪問帶寬都是評價存儲器性能好壞的兩個重要指標(biāo)，存儲容量擴(kuò)大、訪問帶寬提升是如今存儲器發(fā)展的趨勢。單個硬盤、單片內(nèi)存芯片受制于工藝水平，其性能提升十分有限。目前內(nèi)存采取多片芯片堆疊連接的方法來提升性能，多片芯片既可以用于擴(kuò)展內(nèi)存的地址位，又可以用于擴(kuò)展數(shù)據(jù)位，當(dāng)用于擴(kuò)展地址位時可以實現(xiàn)存儲容量的成倍擴(kuò)大，當(dāng)用于擴(kuò)展數(shù)據(jù)位時可以在實現(xiàn)容量擴(kuò)大的同時實現(xiàn)訪問帶寬的提升。而目前硬盤大多采用獨(dú)占總線帶寬的點對點連接方式，這種連接方式非常不適合堆疊連接，使得硬盤容量的擴(kuò)大和帶寬的提升十分不方便。 云是網(wǎng)絡(luò)上基于虛擬化資源的并行處理，本文將云架構(gòu)引入硬盤的設(shè)計，，以實現(xiàn)硬盤結(jié)點的并行處理，從而完成對硬盤容量的擴(kuò)大與帶寬的提升。首先構(gòu)建了一種可堆疊連接的SATA硬盤，用作存儲的虛擬化資源結(jié)點，有效地解決了硬盤堆疊連接困難的問題；然后從以太網(wǎng)特征抽象出只寫總線BoW和統(tǒng)一結(jié)點接口UNI，任何設(shè)備或端口必須通過UNI連接到只寫總線BoW，由UNI負(fù)責(zé)設(shè)備或端口之間無差錯地傳輸消息，從而建立了一種存儲的網(wǎng)絡(luò)架構(gòu)；m個SATA硬盤結(jié)點通過UNI掛接到BoW總線上形成單路堆疊連接SATA硬盤，單路堆疊連接SATA硬盤可實現(xiàn)m倍的存儲容量擴(kuò)大，一個由n路堆疊連接SATA硬盤構(gòu)成的大容量高帶寬硬盤在實現(xiàn)m×n倍容量擴(kuò)大的同時，可以實現(xiàn)n倍帶寬提升。 系統(tǒng)以SATA硬盤為存儲介質(zhì)結(jié)點，用1片Xilinx公司的Zynq-7045芯片和10片Marvell公司的88SE9235芯片搭建。每片88SE9235連接4個SATA硬盤形成1路硬盤，各路硬盤通過PCIe接口連接到Zynq-7045上形成一個具有40個硬盤結(jié)點的大容量高帶寬硬盤，在容量擴(kuò)展同時實現(xiàn)帶寬提升。 系統(tǒng)設(shè)計了傳輸速率達(dá)12.5Gb/s的下一代SATA接口作為對外主機(jī)接口，同時設(shè)計了1個萬兆以太網(wǎng)接口來提供系統(tǒng)網(wǎng)絡(luò)接入能力。
[Abstract]:As an information storage component, memory is an important part of all computer systems, and its performance directly affects the performance of the whole computer system.Storage capacity and access bandwidth are two important indexes to evaluate memory performance. The expansion of storage capacity and the improvement of access bandwidth are the trends of memory development.Single hard disk, single memory chip is subject to the process level, its performance improvement is very limited.At present, multi-chip stacking connection is used to improve the performance of memory. Multi-chip chips can be used to expand memory address bits and data bits, and the storage capacity can be multiplied when used to expand address bits.When used to expand data bits, access bandwidth can be increased while capacity is expanded.At present, the hard disk mostly adopts the point-to-point connection mode which has exclusive bus bandwidth. This connection mode is not suitable for stacking connection, which makes the expansion of hard disk capacity and the enhancement of bandwidth very inconvenient.Cloud is the parallel processing based on virtualized resources on the network. In this paper, the cloud architecture is introduced into the design of hard disk to realize the parallel processing of hard disk nodes, so as to achieve the expansion of hard disk capacity and the enhancement of bandwidth.Firstly, a stacked SATA hard disk is constructed, which can be used as a storage virtual resource node, which effectively solves the problem of hard disk stacking connection.Then the write-only BoW and the unified node interface (Uni) are abstracted from the Ethernet features. Any device or port must be connected to the write-only bus BoW via UNI, and the UNI is responsible for transmitting messages between devices or ports without error.Thus, a storage network architecture named SATA hard disk node is established, which is connected to the BoW bus by UNI to form a single stack connection SATA hard disk. The single stack connection SATA hard disk can achieve m times the storage capacity expansion.A large capacity and high bandwidth hard disk composed of n-channel stacked and connected SATA hard disk can realize the expansion of m 脳 n times capacity and the increase of n times bandwidth at the same time.The system takes SATA hard disk as storage medium node, and uses one Zynq-7045 chip of Xilinx Company and 10 88SE9235 chips of Marvell Company.Each 88SE9235 connects 4 SATA hard disks to form a hard disk. Each hard disk is connected to the Zynq-7045 by PCIe interface to form a large capacity high-bandwidth hard disk with 40 hard disk nodes. The bandwidth is enhanced at the same time of capacity expansion.The next generation SATA interface with transmission rate up to 12.5Gb/s is designed as the external host interface, and a Gigabit Ethernet interface is designed to provide the system network access capability.
【學(xué)位授予單位】：太原理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP333.35

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本文編號：1707543