本文選題：串行高技術附件　切入點：高速串行收發(fā)器　出處：《太原理工大學》2013年碩士論文

【摘要】：隨著集成電路性能的提高和網絡技術的發(fā)展,數據規(guī)�？涨芭蛎�,海量存儲逐漸成為研究的重要課題。以計算機的硬盤為例,處理器的工作頻率不斷加快,并行接口(PATA)的信號之間干擾日益加劇,無法再滿足時代的需要。串行傳輸應運而生,Serial ATA接口管腳少,傳輸速率快,設置多重數據糾錯模式,支持熱插拔特性,剛一出世便成為硬盤存儲業(yè)的新寵。但該產品的關鍵技術大都集中在國外的壟斷公司手中,國內主要對其分析修改,二次開發(fā)。鑒于SATA控制器市場空白,本文以此為切入點,設計面向FPGA的SATA主機控制器,旨在快捷便利地存儲數據。 SATA標準為國外發(fā)布的協(xié)議,本文詳細剖析了SATA1.0版本,深刻理解串行傳輸的層次架構,自上而下為命令層、傳輸層、鏈路層和物理層。設計采用FPGA自頂向下的模塊化理念,以協(xié)議內容為框架,最大限度地發(fā)揮FPGA并行優(yōu)勢,命令層由FPGA的嵌入式處理器MicroBlaze來實現,主要完成硬盤的參數配置和讀寫命令。下面三層為設計重點,中間傳輸層和鏈路層主要完成幀的封裝,幀的發(fā)送、暫停、結束控制,幀的解析和校驗。按功能分為控制模塊和數據通路,前者用VHDL描述為多個狀態(tài)機協(xié)同控制實現,后者調用存儲IP核FIFO保存數據,利用CRC和擾碼校驗雙重數據糾錯。最底層物理層包括高速串行收發(fā)器、OOB信號控制模塊和速率協(xié)調模塊。高速串行收發(fā)器對應協(xié)議中的模擬前端,可根據需求靈活配置8B/10B編解碼,串并轉換,COMMA字符檢測,時鐘修正,預加重和線性均衡等選項。OOB控制模塊和速率協(xié)調模塊能夠自動識別硬盤的傳輸速率,實現了1.5Gbps/3.0Gbps自動切換的串行傳輸通路。 整個設計使用Xilinx公司的ISE軟件完成,各個模塊附有仿真圖和結果分析。系統(tǒng)驗證采用Virtex-5開發(fā)板,把SATA控制器封裝成IP核掛在PLB總線上,由處理器MicroBlaze設置硬盤命令,通過PLB,總線調配SATA控制器IP核對硬盤進行讀寫測試,結果符合協(xié)議要求。整個SATA控制器在FPGA上實現,集成度強、可移植性高,具有很好的工程和市場價值,在計算機存儲領域具有重要意義。
[Abstract]:With the improvement of the performance of integrated circuits and the development of network technology, the data scale is expanding unprecedentedly. Mass storage is becoming an important research topic. Taking the hard disk of the computer as an example, the working frequency of the processor is speeding up. The interference between parallel interface (PATAA) signals is becoming more and more serious, which can no longer meet the needs of the times. Serial ATA interface has fewer pins, faster transmission rate, set up multiple data error correction mode, and support hot-plug characteristics. As soon as it was born, it became a new favorite of hard disk storage industry. However, the key technology of this product is mostly concentrated in the hands of foreign monopoly companies, and it is mainly analyzed and modified in our country. In view of the blank market of SATA controller, this paper takes this as the starting point. A SATA host controller for FPGA is designed to store data quickly and conveniently. The SATA standard is a protocol published abroad. This paper analyzes the SATA1.0 version in detail, deeply understands the hierarchical architecture of serial transmission, from top to bottom for command layer, transport layer, link layer and physical layer. The design adopts the idea of FPGA top-down modularization. Taking the protocol content as the frame, taking the FPGA parallel advantage to the maximum extent, the command layer is realized by the embedded processor MicroBlaze of FPGA, which mainly completes the parameter configuration of the hard disk and the command of reading and writing. The following three layers are the key points of the design. The intermediate transport layer and link layer mainly complete frame encapsulation, frame transmission, pause, end control, frame resolution and verification. The latter calls to store IP core FIFO to save data, uses CRC and scrambling code to check dual data error correction. The bottom layer of physical layer includes high speed serial transceiver OOB signal control module and rate coordination module. 8B/10B codec, serial-parallel conversion, clock correction, preweighting and linear equalization options. OOB control module and rate coordination module can automatically identify the transmission rate of hard disk. The serial transmission path of 1.5Gbps/3.0Gbps automatic switching is realized. The whole design is completed by ISE software of Xilinx Company, each module is accompanied by simulation diagram and result analysis. System verification adopts Virtex-5 development board, encapsulates the SATA controller into IP core and hangs on PLB bus, and the processor MicroBlaze sets the hard disk command. The whole SATA controller is implemented on FPGA with strong integration, high portability and good engineering and market value. It is of great significance in the field of computer storage.
【學位授予單位】：太原理工大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332;TN791

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本文編號：1695219