本文選題：PCIe　切入點：Sora　出處：《北京郵電大學(xué)》2014年碩士論文

【摘要】：隨著無線通信技術(shù)的發(fā)展,軟件無線電(SDR)技術(shù)逐漸成為研究者的關(guān)注熱點。SDR技術(shù)將硬件實現(xiàn)的無線通信協(xié)議搬移到軟件中實現(xiàn),不僅簡化了硬件系統(tǒng)的設(shè)計,還可實現(xiàn)硬件平臺通用和軟件靈活重配的目的。軟件無線電平臺要求數(shù)字信號被及時傳輸?shù)杰浖羞M行處理,同時還要求及時的反饋能力,這需要一個軟硬件之間的高速數(shù)據(jù)傳輸通道。PCI-Express (PCIe)作為最新的總線接口標準,具備承擔(dān)SDR硬件平臺的數(shù)據(jù)傳輸任務(wù)的能力,還有足夠的傳輸帶寬余量用于未來的系統(tǒng)升級。因此,本論文基于微軟Sora SDR平臺設(shè)計了基于PCIe總線的高速數(shù)據(jù)傳輸通道,還完成了數(shù)據(jù)存儲的設(shè)計方案和算法實現(xiàn)。 論文首先實現(xiàn)了基于Xilinx PCIe IP核的高速數(shù)據(jù)傳輸接口設(shè)計。任務(wù)內(nèi)容主要包括Sora硬件平臺PCIe接口的鏈路訓(xùn)練驗證,IP核事物層邏輯設(shè)計和直接內(nèi)存存取(DMA)控制器設(shè)計。DMA控制器的功能是完成數(shù)據(jù)包的分流處理,請求與應(yīng)答和高速數(shù)據(jù)傳輸。 其次,針對硬件接口實現(xiàn)了Linux下的驅(qū)動設(shè)計。PCIe設(shè)備在Linux平臺下屬于字符設(shè)備,作者基于字符驅(qū)動框架完成了對硬件平臺PCIe設(shè)備的讀寫功能,輸入輸出(I/O)控制以及物理內(nèi)存向設(shè)備空間的映射；驅(qū)動為上層用戶提供了訪問設(shè)備的接口,基于這些接口,利用開源MPrace軟件庫,實現(xiàn)了應(yīng)用層對設(shè)備的訪問并完成了論文設(shè)計的系統(tǒng)測試,有效的推動了依托項目的順利實施。 最后,利用驅(qū)動接口和MPrace相關(guān)函數(shù)實現(xiàn)了數(shù)據(jù)存儲算法。該算法采用循環(huán)內(nèi)存讀寫,以讀寫線程并發(fā)執(zhí)行來實現(xiàn)數(shù)據(jù)實時保存,同時提出了更高速的磁盤陣列(RAID)陣列擴展方案。作者進行了大量的測試工作,根據(jù)測試結(jié)果分析了DMA讀寫的時序邏輯,給出了正確性判斷。
[Abstract]:With the development of wireless communication technology, Software Radio SDR (SDR) technology has gradually become the focus of attention of researchers. SDR technology moves the wireless communication protocol implemented by hardware into software, which not only simplifies the design of hardware system, but also simplifies the design of hardware system. The software radio platform requires the digital signal to be transmitted to the software in time for processing, and also requires the timely feedback ability. This requires a high-speed data transfer channel between hardware and software. PCI-Express / PCI) as the latest bus interface standard, with the ability to undertake the task of data transmission on the SDR hardware platform, and sufficient bandwidth allowance for future system upgrades. In this paper, a high speed data transmission channel based on PCIe bus is designed based on Microsoft Sora SDR platform, and the design scheme and algorithm implementation of data storage are also completed. The design of high speed data transmission interface based on Xilinx PCIe IP core is implemented in this paper. The task includes link training verification of PCIe interface of Sora hardware platform and logic design of IP core and direct memory access (DMA) controller. The function of the DMA controller is to complete the data packet shunt processing, Request and reply and high speed data transmission. Secondly, according to the hardware interface, the driver design under Linux. The PCIe device belongs to the character device under the Linux platform. The author completes the reading and writing function of the hardware platform PCIe device based on the character drive frame. I / O) control and the mapping of physical memory to device space; drivers provide interface access to devices for upper-level users; based on these interfaces, open source MPrace software libraries are used. It realizes the access of application layer to the equipment and completes the system test of the thesis design, which effectively promotes the smooth implementation of the supporting project. Finally, the data storage algorithm is implemented by using driver interface and MPrace correlation function, which uses cyclic memory to read and write, read and write threads to execute concurrently to realize real-time data saving. At the same time, a more high-speed expansion scheme of disk array array is proposed. The author has done a lot of testing work. According to the test results, the sequential logic of DMA reading and writing is analyzed, and the correctness judgment is given.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP333;TN92

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