本文選題：電流模式信號處理　切入點：乘除法器　出處：《廣西師范大學》2012年碩士論文　論文類型：學位論文

【摘要】：隨著電流模式乘除法器的發(fā)展,CMOS電流模式乘除法器的研究和開發(fā)已逐漸成為主流趨勢。CMOS電流模式乘除法器,與BJT乘除法器相比,在信號帶寬、線性度、動態(tài)范圍、信號處理能力等方面都有明顯的優(yōu)勢,因而在信號處理中得到了廣泛的應用,主要可以應用于模糊邏輯控制器、人工神經(jīng)網(wǎng)絡、可編程放大器、調(diào)制器、分相器、電流傳輸器、濾波器、正余弦綜合器、密碼學系統(tǒng)等。對于集成電路設計工程師來說,CMOS電流乘除法器可以作為非常有用的集成電路設計基本模塊。 基于平方根電路和平方/除法器電路設計的CMOS電流模式乘除法器具有線性度好、低功耗、結(jié)構簡單、帶寬寬、精度高等特點,在CMOS電流模式乘除法器中較具發(fā)展?jié)摿�。本論文研究了平方根和平�?除法器的電路實現(xiàn)及基于平方根電路和平方／除法器電路的CMOS電流模式乘除法器電路的設計與實現(xiàn)及其在模擬調(diào)幅器、可編程電流放大器、電調(diào)諧第二代電流傳輸器(ECCⅡ)等中的應用。本論文完成的工作及創(chuàng)新點主要包括： (1)以MOS管構成的跨導線性環(huán)路為基礎,設計出電流模平方根電路以及平方／除法器電路,將平方根電路和平方/除法器電路連接起來,實現(xiàn)了一種新型高頻高線性CMOS跨導線性電流模乘除法器電路。對提出的CMOS電流乘除法器的電路,使用CMOSO.35μm工藝參數(shù),進行了HSPICE仿真。結(jié)果表明,該乘除法器電路能很好實現(xiàn)乘除法運算等功能。仿真結(jié)果證實了,提出的電路具有良好的線性特性、高頻特性。該電路在3V的電源電壓下工作時,-3dB帶寬可達到35.1MHz,電源靜態(tài)功耗為202.68μ W,輸出電流范圍為0～25.1μ A,非線性誤差為0.85%,總諧波失真為0.14%。提出的乘除法器電路與Tanno、Lopez等提出的基于跨導線性原理的乘除法器電路相比,優(yōu)點在于-3dB帶寬提高了,功耗降低了,電源電壓降低了,線性度提高了,并且采用了相對更先進的0.35μmCMOS工藝,可節(jié)約芯片面積。 (2)以上述提出的CMOS電流乘除法器電路為基礎,電路結(jié)構及元件參數(shù)不變,對輸入、輸出信號進行選擇,實現(xiàn)了提出的乘除法器在模擬調(diào)幅器、可編程電流放大器等中的應用。通過HSPICE軟件仿真測試,證實了提出的應用方案的正確性。 (3)研究了一種新型簡易CMOS電流乘除法器的電路及其在電流傳輸器電路設計中的應用。該電流模乘除法器電路同樣是基于平方根電路和平方/除法器電路而組建成的,以此電路為基礎,將該電路作為核心電路,加以應用,實現(xiàn)了可編程電流放大器,然后搭建電壓到電流轉(zhuǎn)換器、電流鏡等其他電路,實現(xiàn)了一種新型的基于可編程電流放大器的CMOS第二代電調(diào)諧電流傳輸器ECCⅡ。該電路工作在很低的電源電壓(±1.2V)下,電路增益持續(xù)可編程,線性調(diào)諧范圍寬,Z端的輸出阻抗高。這種電流傳輸器的電流傳輸比可以通過調(diào)節(jié)直流偏置電流而精確地控制。該電路采用0.35umCMOS工藝,使用HSPICE軟件仿真。仿真結(jié)果證實了提出的ECCⅡ在線性度、頻響、電調(diào)諧性和功耗方面具有良好的性能。
[Abstract]:With the development of the current mode multiplier AD633ARZ, research and development of CMOS current mode multiplier AD633ARZ has gradually become the mainstream trend of.CMOS current mode multipliers / dividers, compared with BJT in the multiplying unit, signal bandwidth, linearity, dynamic range, signal processing ability and other aspects have obvious advantages, so it has been widely used in signal processing, mainly used in fuzzy logic controller, artificial neural network, programmable amplifier, modulator, phase splitter, current conveyor filter, sine and cosine synthesizers, cryptography system. For integrated circuit design engineers, CMOS current multiplier AD633ARZ integrated circuit can be used as useful design basic modules.
Square and square root circuit / divider circuit design based on CMOS current mode multiplier divider has good linearity, low power consumption, simple structure, wide bandwidth, high accuracy, more development potential in the CMOS current mode multipliers / dividers. This paper studies the square root and square / divider circuit and current based on CMOS design model of square root circuit and multiplier divider circuit circuit and divider / square and its implementation in analog amplitude modulator, programmable current amplifier, electrically tunable second generation current conveyor (ECC II) application. The work and innovation of this paper mainly includes the complete:
(1) to MOS translinear loop is constituted based on Design of current mode circuit and divider / square square root circuit, connecting the square root circuit and square / divider circuit, the realization of a new high frequency linear CMOS translinear current mode multiplier AD633ARZ circuit. The proposed CMOS current division circuit the instruments, using CMOSO.35 m process parameters, HSPICE simulation was carried out. The results show that the multiplier divider circuit can realize multiplication and division functions. Simulation results demonstrate that the proposed circuit has linear characteristics, good high frequency characteristics. The circuit in the power supply voltage of 3V, -3dB bandwidth can reach 35.1MHz power supply, the static power consumption is 202.68 W, the output current range of 0 ~ 25.1 A, the nonlinear error is 0.85%, the total harmonic distortion for multiplier divider circuit and the Tanno 0.14%. proposed by Lopez based on the cross wire Compared with the multiplier AD633ARZ principle circuit, has the advantages of improving -3dB bandwidth, reduce the power consumption, the power supply voltage is reduced, improves the linearity, and the use of 0.35 mCMOS technology is relatively more advanced, can save the chip area.
(2) to CMOS current multiplier AD633ARZ circuit based on the above, the circuit structure and component parameters unchanged, the input, output signal selection is implemented in analog multiplier AD633ARZ modulator, programmable current amplifier in HSPICE. Through software simulation testing, confirmed the validity of the proposed scheme for applications.
(3) the study of a new type of circuit simple CMOS current multiplier divider and its application in current conveyor circuit design. The current mode circuit and multiplier AD633ARZ is also set up a square root circuit and divider / square based circuit, based on the circuit, the circuit as the core circuit, application, implementation programmable current amplifier, then set the voltage to current converter, current mirror and other circuit, realize a programmable current amplifier CMOS second generation current conveyor based on electrically tunable ECC II model. The circuit operates at very low power supply voltage (+ 1.2V), programmable gain circuit for linear tuning range. Wide, high output impedance of the Z terminal. The current transmission current conveyor ratio can be accurately controlled through adjusting the DC bias current. The circuit uses 0.35umCMOS technology, using HSPICE simulation software. The simulation results show that the proposed ECC II has good performance in the aspects of online degree, frequency response, electrical tuning and power consumption.

【學位授予單位】：廣西師范大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332.22;TN402

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本文編號：1609180