本文選題：SystemC　切入點：系統(tǒng)建模　出處：《計算機工程與設(shè)計》2015年04期 　論文類型：期刊論文

【摘要】：為研究系統(tǒng)建模應(yīng)用于處理器架構(gòu)設(shè)計、性能分析的方法,基于SystemC建模語言,提出一種"結(jié)構(gòu)框圖-模塊細化-模型映射"自頂向下規(guī)范化的系統(tǒng)模型建立方法,以此方法建立MIPS(microprocessor without interlocked piped stages)架構(gòu)處理器的周期精確模型。研究用系統(tǒng)級模型進行系統(tǒng)架構(gòu)設(shè)計的方法,分析不同高速緩存Cache的設(shè)計對處理器性能的影響。仿真結(jié)果表明,L1(Level 1)級Cache采用2路或4路、容量在4KB到32KB之間比較合適。
[Abstract]:In order to study the application of system modeling in processor architecture design and performance analysis, based on SystemC modeling language, a top-down normalization method of "structure block diagram, module thinning and model mapping" is proposed. In this way, the cycle exact model of MIPS(microprocessor without interlocked piped piped processor is established, and the method of system architecture design based on system-level model is studied. The effect of different cache Cache design on processor performance is analyzed. The simulation results show that L1 level 1) level 1 Cache adopts 2 or 4 channels, and its capacity is between 4 KB and 32 KB.
【作者單位】： 中國航天科工集團第二研究院706所;
【分類號】：TP332

【參考文獻】

相關(guān)期刊論文 前2條

1 馬秦生;劉源;張寧;楊s，

本文編號：1605979