本文選題：高速接口IP核　切入點：JTAG　出處：《國防科學技術(shù)大學》2012年碩士論文　論文類型：學位論文

【摘要】：目前，為了加快芯片的設(shè)計效率和縮短設(shè)計周期，IP(Intellectual Property)核的可復(fù)用技術(shù)是SoC(System on Chip)設(shè)計的發(fā)展趨勢。尤其是高速接口IP核的復(fù)用，在不清楚其內(nèi)部具體設(shè)計和結(jié)構(gòu)的情況下，只能把它們當成黑盒子，在集成時其輸入輸出端口也被嵌入到SoC中，這樣原本可測的端口就失去了其原有的可控制性和可觀測性，從而變得不可測。這就給高性能CPU的DFT(Design For Testability)集成設(shè)計和驗證帶來了挑戰(zhàn)。 本文的主要工作是：針對一款高性能CPU芯片（FX芯片）中使用的高速接口IP核進行了自身和將它們集成到CPU中后的DFT集成設(shè)計和驗證，包括高速串口硬核PCIE2/SATA2/USB2PHY和可以綜合的高速并口軟核DDR3PHY。先驗證設(shè)計好的JTAG(Joint Test Action Group)、BIST(Built-In Self Test)等功能的正確性，再從JTAG接口加載測試碼啟動BIST邏輯進行內(nèi)外部loopback功能的驗證。分別給出了這些IP核的DFT結(jié)構(gòu)設(shè)計、驗證方法和驗證結(jié)果。本文工作說明了如何確保IP核自身的正確性，，如何使用其進行有效的集成，如何確保所加載的測試碼有效，最終能降低測試難度和測試成本。 本文的創(chuàng)新點和難度體現(xiàn)在如下幾個方面： 1、綜合運用JTAG和BIST技術(shù)進行內(nèi)外部loopback功能的DFT驗證，為驗證高速接口IP核的模擬和數(shù)字路徑提供了有效的方法。通過這種方法，能確保它們收發(fā)功能的正確性。此外，驗證結(jié)果還表明，USB2.0nanoPHY能正常運行在低速、高速和全速BIST三種模式。 2、通過編寫Testbench，驗證了PCIE2PHY中JTAG指令功能的正確性。通過實驗，發(fā)現(xiàn)了提供的PCIE2PHY的USERCODE指令實際實現(xiàn)的是BYPASS的功能，以及DSCAN指令提供的數(shù)據(jù)寄存器位數(shù)有誤，實際應(yīng)為3209位。 3、對DDR3PHY進行綜合后的物理設(shè)計時，由于布局布線不夠合理，使得DDR3PHY的工作頻率會降低。針對這種情況，在驗證時采用降低JTAG的測試時鐘頻率的方法，再去采樣DDR3PHY的數(shù)據(jù)，得到的測試碼仍能使其在測試時正常工作。 本文所做工作已用于FX芯片設(shè)計，且目前FX芯片正處于流片階段，本文的研究工作不僅能確保這些高速接口IP核的DFT結(jié)構(gòu)設(shè)計合理，收發(fā)模塊功能正確，而且對于相關(guān)的工程問題也有借鑒意義。
[Abstract]:At present, in order to speed up the design efficiency of the chip and shorten the design cycle, the reusable technology of IP intellectual property core is the development trend of SoC(System on chip design. They can only be treated as black boxes, and when integrated, their input and output ports are embedded in the SoC, so that otherwise testable ports lose their original controllability and observability. This makes it unfathomable. This poses a challenge to the design and validation of DFT(Design For Testability for high performance CPU. The main work of this paper is to design and verify the high speed interface IP core which is used in a high performance CPU chip (FX chip) and to integrate them into CPU. It includes high speed serial port hard core PCIE2/SATA2/USB2PHY and high speed parallel port soft core DDR3PHY. first verify the correctness of the designed JTAG(Joint Test Action Group in Self Test, etc. Then loading test code from the JTAG interface to start the BIST logic to verify the internal and external loopback functions. The DFT structure design, verification method and verification results of these IP cores are given respectively. The work of this paper shows how to ensure the correctness of the IP core itself. How to use it for effective integration and how to ensure that the loaded test code is effective can reduce the difficulty and cost of testing. The innovation and difficulty of this paper are reflected in the following aspects:. 1. The DFT verification of internal and external loopback functions by using JTAG and BIST technology synthetically provides an effective method for verifying the analog and digital paths of IP cores with high speed interface. By this method, the correctness of their transceiver functions can be ensured. The results also show that USB2.0 nanoPHY can operate in three modes: low speed, high speed and full speed BIST. 2. The correctness of the function of JTAG instruction in PCIE2PHY is verified by writing Testbench.Through experiment, it is found that the USERCODE instruction provided by PCIE2PHY realizes the function of BYPASS, and the number of data registers provided by DSCAN instruction is incorrect, which should be 3209bit. 3. When the physical design of DDR3PHY is synthesized, the working frequency of DDR3PHY will be reduced because the layout and wiring is not reasonable. In view of this situation, the method of reducing the test clock frequency of JTAG is adopted in the verification, and then the data of DDR3PHY is sampled. The obtained test code can still work properly during the test. The work done in this paper has been used in the design of FX chip, and the current FX chip is in the stage of stream chip. The research work in this paper can not only ensure that the DFT structure of the IP core with high speed interface is reasonable, but also the function of the transceiver module is correct. And for the relevant engineering problems also have reference significance.
【學位授予單位】：國防科學技術(shù)大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP334.7;TN47

【參考文獻】

相關(guān)期刊論文 前4條

1 金西,丁文祥,

本文編號：1590254