本文選題：FIFO　切入點(diǎn)：ASIC　出處：《湖南大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：異步FIFO（FirstInFirstOut）是一種先進(jìn)先出的存儲(chǔ)器件，可以實(shí)現(xiàn)在不同時(shí)鐘域之間進(jìn)行數(shù)據(jù)的傳遞。異步FIFO的應(yīng)用場(chǎng)景十分廣泛，不僅能滿足現(xiàn)代國(guó)防、航天航空等領(lǐng)域應(yīng)用的需要，還可用于數(shù)據(jù)采集和圖象處理等其它方面。相比于同步集成電路設(shè)計(jì)，異步集成電路具有低功耗、高性能和便于模塊化設(shè)計(jì)等優(yōu)點(diǎn)，，目前在集成電路的設(shè)計(jì)中已經(jīng)被各大公司所采用。特別是異步時(shí)鐘域數(shù)據(jù)之間的傳輸是一個(gè)重要的問(wèn)題，采用異步FIFO是解決這一問(wèn)題的重要手段。 空/滿信號(hào)的產(chǎn)生以及亞穩(wěn)態(tài)的問(wèn)題是異步FIFO設(shè)計(jì)中的兩個(gè)難點(diǎn)。首先：空/滿信號(hào)的產(chǎn)生，是通過(guò)比較讀寫(xiě)地址指針來(lái)產(chǎn)生的，當(dāng)讀寫(xiě)地址指針相同時(shí)，F(xiàn)IFO無(wú)法確定處于空狀態(tài)還是滿狀態(tài)；其次：亞穩(wěn)態(tài)問(wèn)題，由于讀寫(xiě)地址處于不同的時(shí)鐘域之中，比較之前需要對(duì)地址進(jìn)行同步，由于地址指針是多位的，在同步過(guò)程中不可避免的會(huì)產(chǎn)生亞穩(wěn)態(tài)的問(wèn)題。 針對(duì)存在的兩個(gè)問(wèn)題，本設(shè)計(jì)通過(guò)采用地址附加位和格雷碼指針代替二進(jìn)制碼地址的方式進(jìn)行了有效的解決，即在讀寫(xiě)地址前增加一位附加位來(lái)判斷是空狀態(tài)還是滿狀態(tài)。在空滿狀態(tài)的界定時(shí)增加了保留空間（Reserve）這一參數(shù)，從而增強(qiáng)了FIFO的穩(wěn)定性。采用格雷碼指針代替二進(jìn)制碼地址，并且采用可配置的同步電路解決這一問(wèn)題。還通過(guò)對(duì)FIFO時(shí)鐘進(jìn)行合理的利用，在讀寫(xiě)控制模塊不工作時(shí)，相應(yīng)的時(shí)鐘停止，直到開(kāi)始工作時(shí)，時(shí)鐘重新啟動(dòng)，從而滿足了高效率的要求。 本設(shè)計(jì)模塊采用VerilogHDL代碼進(jìn)行編寫(xiě)，使用SynopsysVCS進(jìn)行功能通讀仿真，并用Xilinx的FPGA進(jìn)行功能驗(yàn)證，由于本FIFO設(shè)計(jì)模塊是話音處理器分合路模塊的一部分，將與其他模塊整合在一起，綜合及布局布線采用中芯國(guó)際（SMIC）0.18μmCMOS工藝庫(kù)，最終根據(jù)項(xiàng)目要求實(shí)現(xiàn)了流片。通過(guò)實(shí)際測(cè)試結(jié)果表明：該話音處理器的計(jì)算誤差低于4%；在工作電壓為1.8V的情況下，其平均功耗約為1.18mW/MHz，本設(shè)計(jì)在穩(wěn)定性、功耗、速度上都達(dá)到了預(yù)期的要求。
[Abstract]:Asynchronous FIFO (first in first output) is a kind of first in first out memory device, which can transfer data between different clock domains. Asynchronous FIFO is widely used in many fields, which can not only meet the needs of modern defense, aerospace and other applications. It can also be used in data acquisition and image processing. Compared with synchronous integrated circuit design, asynchronous integrated circuit has the advantages of low power consumption, high performance and easy modular design. At present, the design of integrated circuits has been adopted by many companies, especially the transmission between asynchronous clock domain data is an important problem, the use of asynchronous FIFO is an important means to solve this problem. The generation of empty / full signal and the problem of metastable state are two difficulties in asynchronous FIFO design. Firstly, the generation of empty / full signal is produced by comparing the read and write address pointer. When the read-write address pointer is the same, the FIFO can not determine whether it is empty or full. Secondly, the metastable problem, because the read-write address is in different clock fields, the address needs to be synchronized before comparison, because the address pointer is multi-bit. The problem of metastable state is inevitable in the process of synchronization. In order to solve the two problems, the method of adding address bit and Graycode pointer instead of binary code address is used to solve the problem. That is, adding an additional bit before reading and writing to determine whether the empty state is empty or full. The parameter of reserved space is added in the definition of empty full state, which enhances the stability of FIFO. The gray code pointer is used instead of binary code address. And the configurable synchronous circuit is used to solve this problem. Through the reasonable use of the FIFO clock, the corresponding clock stops when the read-write control module does not work, and the clock restarts when it starts to work. Thus, it meets the requirement of high efficiency. This design module uses VerilogHDL code to write, uses SynopsysVCS to carry on the function read through the emulation, and uses the Xilinx FPGA to carry on the function verification, because this FIFO design module is a part of the voice processor divider module, will integrate with the other modules together, The synthesis and layout wiring is based on the SMIC SMIC 0.18 渭 mCMOS process library. Finally, the flow sheet is realized according to the requirements of the project. The actual test results show that the calculation error of the voice processor is less than 4 parts, and the working voltage is 1.8 V. The average power consumption is about 1.18mW / MHz. the design meets the expected requirements in terms of stability, power consumption and speed.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333

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