本文選題：DDR　切入點：SDRAM　出處：《西安電子科技大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：現(xiàn)代電子產(chǎn)品隨著技術(shù)的迅速發(fā)展已呈現(xiàn)多樣化，在各類的電子產(chǎn)品中均追求著多功能、高性能、低功耗，而整個產(chǎn)品對其主存儲設(shè)備要求也是越來越高。DDR SDRAM（Double Data Rate SDRAM，雙倍數(shù)據(jù)率同步動態(tài)隨機存儲器）以其高速率、大容量和良好的兼容性在這些需求存儲設(shè)備的領(lǐng)域得到了相當(dāng)廣泛的應(yīng)用。針對不同的系統(tǒng)要求，在選擇器存儲單元時有不同的取舍，比如，高性能計算機，其要求高頻率以及高帶寬，這樣DDRII或者DDRIII都是很不錯的選擇，但是對嵌入式為系統(tǒng)而言，高性能就不是唯一的要求，其成本和穩(wěn)定性也必須考慮在其中，經(jīng)過綜合考慮還是選擇DDR SDRAM芯片，DDRIII成本太高，DDRII對電路板的要求很高，即在制作能夠適用DDRII的電路板的成本就比較高。所以就目前而言雖然DDRII和DDRIII在性能方面有一定的優(yōu)勢，但以其高成本，人們在選擇嵌入式的存儲單元時還是傾向于DDR SDRAM。而DDR SDRAM和外設(shè)間需要一個橋梁，DDR SDRAM控制器正是起著這一重要的作用，所以研究設(shè)計DDRSDRAM控制器的設(shè)計有著極其重要的價值和意義。 本文首先介紹了DDR SDRAM存儲器的工作原理，在此基礎(chǔ)之上給出了DDRSDRAM的指令以及典型的操作時序；按照J(rèn)EDEC工業(yè)標(biāo)準(zhǔn)給定的時序要求對DDRSDRAM進行了總體模塊的設(shè)計以及各小模塊的劃分，重點對DDR SDRAM的關(guān)鍵技術(shù)進行了詳細的分析；采用自頂而下的設(shè)計方法，用Verilog HDL硬件描述語言進行控制器的實現(xiàn)，最后用仿真工具進行了前仿真和后續(xù)仿真，用Xilinx ISE進行了綜合和布局布線，通過驗證表明控制器的設(shè)計達到了預(yù)期的設(shè)計要求，符合一定的設(shè)計的規(guī)范。 本文設(shè)計的控制器接口簡潔，充分利用了FPGA中時鐘管理資源，使得設(shè)計的復(fù)雜程度有一定的簡化，，而且設(shè)計中的操作簡單又能滿足特定的DDR SDRAM控制，具有很強的適用性。
[Abstract]:With the rapid development of technology, modern electronic products have been diversified, and they are pursuing multifunction, high performance and low power consumption in all kinds of electronic products. The demand of the whole product for its main storage device is also getting higher and higher. DDR SDRAM(Double Data Rate SDRAM, double data rate synchronous dynamic random access memory (DRAM) with its high speed, Large capacity and good compatibility are widely used in these areas of demand storage devices. For different system requirements, there are different trade-offs when selecting storage units, such as high-performance computers, It requires high frequency and high bandwidth, so DDRII or DDRIII is a good choice, but for embedded systems, high performance is not the only requirement, its cost and stability must also be considered. After comprehensive consideration or selection of DDR SDRAM chip, the cost of DDR III is too high. The cost of making a circuit board that can be applied to DDRII is very high, that is, the cost of making a circuit board that can be applied to DDRII is relatively high. So at present, although DDRII and DDRIII have some advantages in performance, However, because of its high cost, people still prefer DDR SDRAM when they choose embedded memory cells. The need for a bridge between DDR SDRAM and peripheral devices plays this important role. So it is of great value and significance to study the design of DDRSDRAM controller. This paper first introduces the working principle of DDRSDRAM memory, and then gives the instruction of DDRSDRAM and the typical operation timing. According to the timing requirement of JEDEC industry standard, the overall module design and the partition of each module are carried out, the key technology of DDRSDRAM is analyzed in detail, and the top-down design method is adopted. The controller is implemented with Verilog HDL hardware description language. Finally, the pre-simulation and follow-up simulation are carried out with simulation tools, and the synthesis and layout routing with Xilinx ISE are carried out. The verification results show that the controller design meets the expected design requirements. Conform to certain design specifications. The controller designed in this paper is simple in interface, makes full use of the clock management resources in FPGA, simplifies the complexity of the design, and the operation in the design is simple and can satisfy the specific DDR SDRAM control, so it has strong applicability.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333

【引證文獻】

相關(guān)碩士學(xué)位論文 前1條

1 唐杏;基于嵌入式的測試技術(shù)實驗教學(xué)平臺軟件模塊設(shè)計[D];電子科技大學(xué);2013年

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