本文關(guān)鍵詞： Petri網(wǎng) 專用指令集處理器 流水線 PNML　出處：《武漢紡織大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：專用指令集處理器(ASIP)是一種新型的具有處理器結(jié)構(gòu)的芯片，具有可定制性，應(yīng)用在某些特定領(lǐng)域，通過功能定制，能對嵌入式系統(tǒng)進(jìn)行優(yōu)化，提高嵌入式設(shè)備的執(zhí)行效率，隨著嵌入式領(lǐng)域的發(fā)展，ASIP得到了廣泛應(yīng)用。 隨著ASIP應(yīng)用面的擴(kuò)大，對ASIP的設(shè)計周期，設(shè)計成本等非功能性要求越來越高，而流水線結(jié)構(gòu)層設(shè)計是ASIP設(shè)計中最復(fù)雜的部分之一，傳統(tǒng)的ASIP流水線設(shè)計方法已經(jīng)無法滿足要求，本文針對傳統(tǒng)設(shè)計方法設(shè)計周期長，更改底層邏輯的工作量大的不足，探討了一種基于“描述-綜合”的設(shè)計方法學(xué)，對ASIP流水線微結(jié)構(gòu)進(jìn)行建模，用可執(zhí)行描述語言對模型描述，通過邏輯綜合，生成RTL級的HDL描述，采用這種設(shè)計方式，能快速的對流水線結(jié)構(gòu)驗證和優(yōu)化，，更改流水線結(jié)構(gòu)只需要修改上層的模型描述，自動映射生成下層流水線結(jié)構(gòu)，減少了設(shè)計者工作量，縮短了ASIP設(shè)計周期。 本文遵循“描述-綜合”的設(shè)計方法學(xué)，采用Petri網(wǎng)對ASIP流水線進(jìn)行建模，給出了三種不同架構(gòu)的流水線Petri網(wǎng)模型，用可執(zhí)行的PNML(Petri網(wǎng)標(biāo)記語言)描述語言對流水線模型進(jìn)行描述，利用自行設(shè)計完成的流水線集成開發(fā)環(huán)境，對OTA架構(gòu)的流水線模型進(jìn)行動態(tài)仿真驗證，完成邏輯綜合后，Petri網(wǎng)流水線模型的PNML描述映射成為RTL級的HDL描述，通過Altera QuartusⅡ?qū)DL代碼進(jìn)行調(diào)試，仿真。最后下載到FPGA（CycloneⅢ系列）開發(fā)板運(yùn)行觀察結(jié)果。
[Abstract]:ASIP (Special instruction set processor) is a new type of chip with processor architecture, which can be used in some special fields. Through function customization, embedded system can be optimized and the execution efficiency of embedded device can be improved. With the development of embedded field, ASIP has been widely used. With the expansion of ASIP application area, the non-functional requirements of ASIP design cycle, design cost and so on are becoming higher and higher. Pipeline structural layer design is one of the most complex parts in ASIP design. The traditional ASIP pipeline design method has been unable to meet the requirements. This paper discusses a design methodology based on "description and synthesis", aiming at the shortage of long design period and heavy workload of changing the underlying logic in the traditional design method. Modeling the ASIP pipeline microstructure, describing the model with executable description language, generating RTL level HDL description by logic synthesis, using this design method, we can quickly verify and optimize pipeline structure. Changing pipeline structure only needs to modify the model description of the upper layer, and automatically map to generate the lower-layer pipeline structure, which reduces the designer's workload and shortens the ASIP design cycle. In this paper, according to the design methodology of "description and synthesis", ASIP pipeline is modeled by using Petri net, and three kinds of pipeline Petri net models with different structures are given. Pipeline model is described by using executable PNML(Petri net markup language (PNML(Petri net markup language), and by using the integrated development environment of pipeline, which is designed and completed by ourselves, a dynamic simulation is carried out to verify the pipeline model of OTA architecture. The PNML description of pipeline model of logic synthesis is mapped to RTL level HDL description. The HDL code is debugged and simulated by Altera Quartus 鈪

本文編號：1547960