本文關鍵詞： MTV體系結構 模擬器 多線程 向量　出處：《國防科學技術大學》2012年碩士論文　論文類型：學位論文

【摘要】：隨著單核微體系結構的不斷改進，程序的指令級并行性已基本上開發(fā)殆盡，目前國際上微處理器的主要發(fā)展方向是發(fā)掘程序的任務級并行性和數(shù)據(jù)級并行性。本文試圖在傳統(tǒng)的單核體系結構基礎上，深入發(fā)掘任務級并行性和數(shù)據(jù)級并行性，從多個層面提升微處理器性能。本文提出了面向科學計算的眾線程寬向量（Many-Thread wide Vector，MTV）體系結構，能夠同時開發(fā)程序的指令級并行性、任務級并行性和數(shù)據(jù)級并行性。 本文的主要工作包括兩個方面，即MTV體系結構建模和MTV體系結構的性能分析。 首先，本文對MTV體系結構進行了功能建模和性能建模，，形成了一款執(zhí)行驅(qū)動的MTV體系結構全系統(tǒng)模擬器。功能建模方面，該模擬器建模了MTV體系結構的寄存器、存儲器和指令執(zhí)行引擎，支持引導未經(jīng)修改的操作系統(tǒng)，并且采用了指令譯碼緩沖和地址翻譯緩沖等多種優(yōu)化技術提升性能。性能模擬方面，建模了一條支持硬件多線程的亂序執(zhí)行流水線，建模了分支預測、亂序執(zhí)行、硬件多線程、Cache層次和片上互連網(wǎng)絡等多種微體系結構部件。MTV模擬器采用模塊化設計思想，利用動態(tài)鏈接技術，實現(xiàn)了模擬器各部件模型的動態(tài)加載，使得模擬器具有很高的靈活性。 其次，本文在MTV模擬器內(nèi)實現(xiàn)了一個片上存儲系統(tǒng)的Profiling框架，并在此基礎上對MTV體系結構的存儲系統(tǒng)進行了初步研究和性能分析，包括多線程對訪存延遲的容忍程度和向量存儲對存儲結構的影響兩個方面�；趯嶒灁�(shù)據(jù)的分析，提出了一種適合標量和向量混合存儲的存儲器改進方案，并進行了一定的性能分析。
[Abstract]:With the continuous improvement of the single-core microarchitecture, the instruction level parallelism of the program has basically been developed. At present, the main development direction of microprocessor in the world is to explore the task level parallelism and data level parallelism of programs. This paper attempts to explore the task level parallelism and data level parallelism on the basis of the traditional single core architecture. In this paper, we propose a multithread wide vector many-Thread wide VectorMTV architecture for scientific computing, which can simultaneously develop the command level parallelism, task level parallelism and data level parallelism of programs. The main work of this paper includes two aspects: modeling of MTV architecture and performance analysis of MTV architecture. First of all, the function modeling and performance modeling of MTV architecture are carried out, and an executive-driven MTV architecture full-system simulator is formed. In terms of functional modeling, the simulator models the register of MTV architecture. Memory and instruction execution engine, supporting the boot of unmodified operating system, and using a variety of optimization techniques such as instruction decoding buffer and address translation buffer to improve performance. In this paper, we model pipeline, which supports hardware multithreading, model branch prediction, scramble execution, hardware multithreading Cache hierarchy and on-chip interconnection network. MTV simulator adopts modularization design idea. The dynamic link technology is used to realize the dynamic loading of each component model of the simulator, which makes the simulator have high flexibility. Secondly, a Profiling framework of on-chip storage system is implemented in the MTV simulator, and the storage system of MTV architecture is studied and analyzed on this basis. This paper includes two aspects: the tolerance of multithreading to memory access delay and the effect of vector storage on memory structure. Based on the analysis of experimental data, a memory improvement scheme suitable for scalar and vector hybrid storage is proposed. A certain performance analysis was carried out.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332

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