本文關(guān)鍵詞： 新概念動(dòng)態(tài)測(cè)試 高速數(shù)據(jù)傳輸 信號(hào)完整性 電源完整性　出處：《中北大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：微機(jī)技術(shù)和信號(hào)處理技術(shù)的飛速發(fā)展帶動(dòng)了高速數(shù)據(jù)傳輸技術(shù)的革命性飛躍。USB總線技術(shù)已經(jīng)有了量及的變化，傳輸速率從剛出現(xiàn)時(shí)的1.2Mb/s到現(xiàn)在的5Gb/s，僅僅用了二十年的時(shí)間，與此同時(shí)，這樣的飛躍性發(fā)展，還表現(xiàn)在電源管理能力的提升，資源配置的人性化過(guò)程等方面。 新概念動(dòng)態(tài)測(cè)試的出現(xiàn)，對(duì)存儲(chǔ)測(cè)試技術(shù)在存儲(chǔ)容量及傳輸速率方面都提出了更高的要求，技術(shù)成熟的USB二代產(chǎn)品USB2.0數(shù)據(jù)傳輸接口已經(jīng)無(wú)法滿足測(cè)試需求，基于USB3.0的高速數(shù)據(jù)傳輸系統(tǒng)應(yīng)運(yùn)而生�，F(xiàn)階段，實(shí)驗(yàn)室在USB2.0的基礎(chǔ)上，基于USB3.0的高速數(shù)據(jù)傳輸系統(tǒng)的研究已經(jīng)進(jìn)入了設(shè)計(jì)階段。但是，在一些關(guān)鍵問(wèn)題的處理上還存在一定問(wèn)題。如：驅(qū)動(dòng)程序的開(kāi)發(fā)、接口與FPGA的通信、高速PCB板的信號(hào)和電源完整性問(wèn)題等。為了解決這些關(guān)鍵問(wèn)題，，本文在撰寫(xiě)過(guò)程中，不是簡(jiǎn)單的進(jìn)行一些開(kāi)發(fā)板的調(diào)試工作，而是利用Cadence軟件成功繪制系統(tǒng)的原理圖及PCB圖，并進(jìn)行仿真，解決竄擾、反射、電源完整性等問(wèn)題。圍繞課題研究的目的，本文主要做了以下幾方面的工作： 1．總結(jié)了USB2.0接口在應(yīng)用中遇到的幾個(gè)關(guān)鍵問(wèn)題，提出了較為有效的解決方法，并進(jìn)行了仿真驗(yàn)證； 2．分析對(duì)比了幾種高速接口的性能，總結(jié)了USB3.0接口技術(shù)的幾個(gè)優(yōu)勢(shì)，提出了較為可行的設(shè)計(jì)方案，繪制了系統(tǒng)的原理框圖； 3．利用Cadence軟件對(duì)高速數(shù)據(jù)傳輸系統(tǒng)硬件原理圖進(jìn)行了完善，實(shí)現(xiàn)了與FPGA及DDR2的互聯(lián)。在認(rèn)真學(xué)習(xí)了高速PCB設(shè)計(jì)方法的基礎(chǔ)上，針對(duì)信號(hào)反射、信號(hào)竄擾、差分線設(shè)計(jì)、電源完整性幾個(gè)常見(jiàn)問(wèn)題，進(jìn)行了具體的仿真，并提出了有效的設(shè)計(jì)方法，完成了高速數(shù)據(jù)傳輸系統(tǒng)的PCB設(shè)計(jì)工作； 4．對(duì)系統(tǒng)的固件程序及FPGA邏輯控制時(shí)序進(jìn)行了設(shè)計(jì)仿真。在GPIF II接口工作在SLAVE FIFO模式下，對(duì)固件框架進(jìn)行了改進(jìn)，并實(shí)現(xiàn)了與FPGA的通信。 5．完成了系統(tǒng)的硬件、速度、傳輸方向等測(cè)試工作，驗(yàn)證了系統(tǒng)的可行性。
[Abstract]:The rapid development of microcomputer technology and signal processing technology has led to a revolutionary leap in high-speed data transmission technology. USB bus technology has changed in quantity and quantity. The transmission rate has changed from 1.2 Mb / s when it first appeared to 5 GB / s at present, in only 20 years. At the same time, such a leap-forward development, but also in the improvement of power management capacity, the allocation of resources in the process of humanization, and so on. With the emergence of new concept dynamic testing, the storage testing technology has put forward higher requirements in storage capacity and transmission rate. The mature USB second-generation USB2.0 data transmission interface has been unable to meet the test requirements. High-speed data transmission system based on USB3.0 came into being. At present, the research of high-speed data transmission system based on USB3.0 based on USB2.0 in laboratory has entered the stage of design. There are still some problems in dealing with some key problems, such as the development of driver, the communication between interface and FPGA, the signal and power integrity of high speed PCB board, etc. In order to solve these key problems, in the process of writing, Not simply debugging some development boards, but using Cadence software to draw the schematic diagram and PCB diagram of the system successfully, and carry on the simulation to solve the problems of crosstalk, reflection, power integrity and so on. The main work of this paper is as follows:. 1. Several key problems encountered in the application of USB2.0 interface are summarized, and some effective solutions are put forward and verified by simulation. 2. The performance of several high-speed interfaces is analyzed and compared, several advantages of USB3.0 interface technology are summarized, a more feasible design scheme is put forward, and the principle block diagram of the system is drawn. 3. The hardware schematic diagram of high speed data transmission system is perfected by using Cadence software, and the interconnection with FPGA and DDR2 is realized. On the basis of studying the design method of high speed PCB, the signal reflection, signal channeling and differential line are designed. Several common problems of power supply integrity have been simulated and an effective design method has been put forward. The PCB design of high-speed data transmission system has been completed. 4. The firmware program of the system and the timing of FPGA logic control are designed and simulated. The firmware framework is improved in SLAVE FIFO mode with the interface of GPIF II, and the communication with FPGA is realized. 5. The hardware, speed and transmission direction of the system are tested, and the feasibility of the system is verified.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP334.7

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 祖靜,申湘南,張文棟;存儲(chǔ)測(cè)試技術(shù)[J];兵工學(xué)報(bào);1994年04期

2 劉妍秀;;USB3.0體系結(jié)構(gòu)及發(fā)展前景[J];長(zhǎng)春大學(xué)學(xué)報(bào);2010年10期

3 周子琛;申振寧;;高速嵌入式系統(tǒng)中的電源完整性設(shè)計(jì)方法[J];單片機(jī)與嵌入式系統(tǒng)應(yīng)用;2010年03期

4 蘆艷芳;郭林;;USB3.0兼容性與電源分配方案[J];電腦知識(shí)與技術(shù);2010年27期

5 劉宇芳;李秀娟;;Labview平臺(tái)下基于DLL的USB通信技術(shù)應(yīng)用[J];安徽工業(yè)大學(xué)學(xué)報(bào)(自然科學(xué)版);2008年02期

6 蔣冬初;李玉山;;高速PCB中微帶線的串?dāng)_分析[J];海南大學(xué)學(xué)報(bào)(自然科學(xué)版);2009年02期

7 曹燕麗;孟利民;;高速電路中傳輸耦合的反射和串?dāng)_仿真[J];杭州電子科技大學(xué)學(xué)報(bào);2009年05期

8 白同云;;高速PCB電源完整性研究[J];中國(guó)電子科學(xué)研究院學(xué)報(bào);2006年01期

9 劉洪星,謝玉山;Eclipse開(kāi)發(fā)平臺(tái)及其應(yīng)用[J];武漢理工大學(xué)學(xué)報(bào)(信息與管理工程版);2005年02期

10 崔亮飛;;USB總線技術(shù)在大容量存儲(chǔ)測(cè)試系統(tǒng)中的應(yīng)用[J];儀表技術(shù);2010年11期

本文編號(hào)：1532548