本文關(guān)鍵詞： 時(shí)間同步 IEEE1588 最佳主時(shí)鐘算法 時(shí)間戳　出處：《山東大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：中文摘要 隨著變電站的數(shù)字化建設(shè),分布式系統(tǒng)應(yīng)用漸成趨勢。各個(gè)分布系統(tǒng)之間的時(shí)間同步需要由一個(gè)精度高、成本低、簡單易用的時(shí)間同步系統(tǒng)來完成。而且變電站對時(shí)間同步的精度要求越來越高,現(xiàn)有的網(wǎng)絡(luò)對時(shí)技術(shù)如SNTP(Simple Network Time Protocol)等己難以滿足這些要求。IEEE1588精確時(shí)鐘協(xié)議能有效地解決高精度時(shí)間同步的問題。使用該技術(shù)可以在不增加網(wǎng)絡(luò)負(fù)荷的情況下,實(shí)現(xiàn)各個(gè)分布單元的時(shí)間精確同步。如果采用硬件電路的輔助,時(shí)間同步精度最高可以達(dá)到亞微秒級,完全能滿足變電站對時(shí)間同步的要求。 本文詳細(xì)分析了IEEE1588協(xié)議的系統(tǒng)組成、時(shí)鐘同步模型、時(shí)鐘同步原理、最佳主時(shí)鐘算法以及協(xié)議引擎狀態(tài)機(jī),并給出了時(shí)間戳的標(biāo)記方案,為時(shí)間同步系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)奠定了基礎(chǔ)。 本文給山了時(shí)鐘同步系統(tǒng)的軟件設(shè)計(jì)方案,實(shí)現(xiàn)了主控模塊、報(bào)文管理模塊以及最佳主時(shí)鐘算法模塊。本文還闡述了“ARM9+FPGA+MAC+PHY"的硬件設(shè)計(jì)方案。其中,ARM9作為微處理器負(fù)責(zé)IEEE1588協(xié)議的運(yùn)行。FPGA負(fù)責(zé)檢測MAC和PHY之間MII接口上的時(shí)間報(bào)文,生成時(shí)間戳和校準(zhǔn)本地時(shí)鐘。在嵌入式Linux環(huán)境下完成IEEE1588時(shí)間同步系統(tǒng)的軟件開發(fā)和FPGA與DM9000設(shè)備驅(qū)動(dòng)程序的開發(fā),并把整個(gè)系統(tǒng)移植到ARM920T平臺(tái)上,包括Bootloader、Linux內(nèi)核、文件系統(tǒng)以及IEEE1588應(yīng)用程序。最后對最佳主時(shí)鐘算法和時(shí)間同步進(jìn)行測試,給出測試結(jié)果并進(jìn)行分析。
[Abstract]:Chinese abstract. With the digital construction of substation, the application of distributed system is becoming a trend. The time synchronization between each distributed system needs a high precision, low cost, Simple and easy to use time synchronization system to complete. And substation time synchronization accuracy requirements are higher and higher, Existing network timing technologies such as SNTP(Simple Network Time protocol can not meet these requirements. IEEE 1588 precise clock protocol can effectively solve the problem of high precision time synchronization. With the aid of hardware circuit, the precision of time synchronization can reach sub-microsecond level, which can meet the requirement of substation time synchronization. In this paper, the system composition, clock synchronization model, clock synchronization principle, optimal master clock algorithm and protocol engine state machine of IEEE1588 protocol are analyzed in detail, and the marking scheme of timestamp is given. It lays a foundation for the design and implementation of time synchronization system. In this paper, the software design scheme of clock synchronization system is given, and the main control module is realized. This paper also describes the hardware design of "ARM9 FPGA MAC PHY", in which ARM9 is responsible for the running of IEEE1588 protocol as a microprocessor .FPGA is responsible for detecting the time message on the MII interface between MAC and PHY. The software development of IEEE1588 time synchronization system and the development of FPGA and DM9000 device driver are completed under the embedded Linux environment, and the whole system is transplanted to ARM920T platform, including Bootload FPGA kernel. Finally, the optimal master clock algorithm and time synchronization are tested, and the test results are given and analyzed.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP368.1;TP316.81

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