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基于編譯實(shí)現(xiàn)微線程的故障檢測(cè)機(jī)制關(guān)鍵技術(shù)研究

發(fā)布時(shí)間:2018-02-02 19:43

  本文關(guān)鍵詞: 微線程 寄存器窗口 RTL 故障注入 出處:《哈爾濱工業(yè)大學(xué)》2012年碩士論文 論文類型:學(xué)位論文


【摘要】:近年來,隨著容錯(cuò)技術(shù)的發(fā)展,軟件容錯(cuò)技術(shù)作為一種提高軟件可靠性的重要方法越來越引起關(guān)注。軟件容錯(cuò)的主要技術(shù)包括:基于重復(fù)指令的錯(cuò)誤檢測(cè)技術(shù)(EDDI),基于數(shù)字簽名的控制流檢測(cè)(CFCSS)技術(shù)和源到源編譯容錯(cuò)等。它們?cè)诰幾g階段的不同抽象層次對(duì)軟件進(jìn)行加固,生成具有容錯(cuò)性能的應(yīng)用程序。 本文提出的微線程故障檢測(cè)方法也是一種基于編譯的容錯(cuò),它是在編譯階段的中間語言RTL上進(jìn)行,并在SAM模擬器上進(jìn)行故障注入實(shí)驗(yàn)。 首先,本文對(duì)處理器核內(nèi)故障容錯(cuò)方法研究近況進(jìn)行分析,,比較其差異。然后深入研究了UltraSPARC T2平臺(tái),包含架構(gòu)的特點(diǎn),處理器架構(gòu),指令集和traps等方面的內(nèi)容。重點(diǎn)是寄存器窗口的相關(guān)內(nèi)容,包括寄存器窗口的原理和相關(guān)的指令。 接著,本文描述了微線程故障檢測(cè)方案的算法思想和整體設(shè)計(jì)方案。微線程故障檢測(cè)方案可以概括為結(jié)合UltraSPARC T2平臺(tái)的,在編譯器的中間表示層RTL級(jí)別實(shí)現(xiàn)的一種全指令復(fù)制規(guī)則的容錯(cuò)方案。這種方案既不依賴于前端特定的高級(jí)語言,也不依賴于后端的目標(biāo)平臺(tái),因此具有很強(qiáng)的適應(yīng)性。 最后,本文對(duì)微線程方案進(jìn)行詳細(xì)設(shè)計(jì)。這部分首先研究了GCC編譯相關(guān)技術(shù)。深入剖析了GCC編譯過程,重點(diǎn)是從中間表示Gimple Tree到RTL的生成過程,以及RTL優(yōu)化和處理過程,匯編代碼輸出過程。其次,本文從簡(jiǎn)單的賦值表達(dá)式,算術(shù)邏輯運(yùn)算表達(dá)式,特殊的表達(dá)式和函數(shù)調(diào)用等幾種指令類型的處理過程對(duì)微線程的具體實(shí)現(xiàn)進(jìn)行描述。再次,利用故障注入平臺(tái)針對(duì)我們的微線程故障檢測(cè)方案進(jìn)行故障注入實(shí)驗(yàn),并對(duì)實(shí)驗(yàn)結(jié)果進(jìn)行分析。從實(shí)驗(yàn)結(jié)果可以看出,本文提出的基于編譯的微線程故障檢測(cè)技術(shù)在容錯(cuò)性能上有較好的表現(xiàn),并且犧牲的時(shí)間和空間代價(jià)也在合理的范圍內(nèi)。
[Abstract]:In recent years, with the development of fault-tolerant technology. As an important method to improve software reliability, software fault-tolerant technology has attracted more and more attention. The main techniques of software fault tolerance include: error detection based on repeated instructions (EDDI). Control flow Detection (CFCSS) technology based on digital signature and source-to-source compilation fault tolerance are used to reinforce the software at different abstract levels in the compilation stage to generate applications with fault-tolerant performance. The fault detection method proposed in this paper is also a fault tolerance based on compilation. It is implemented on the intermediate language RTL in the compilation stage and the fault injection experiment is carried out on the SAM simulator. Firstly, this paper analyzes the research status of fault tolerance method in processor core and compares its differences. Then, the paper deeply studies the UltraSPARC T2 platform, including the characteristics of architecture and processor architecture. Instruction set and traps. The emphasis is on the register window, including the principle of register window and related instructions. Then, this paper describes the algorithm and the overall design of the micro-thread fault detection scheme, which can be summarized as a combination of UltraSPARC T2 platform. A fault-tolerant scheme for full instruction replication rules implemented at the RTL level in the intermediate presentation layer of the compiler, which does not depend on either the front-end specific high-level language or the back-end target platform. Therefore, it has strong adaptability. Finally, this paper designs the scheme of tasklets in detail. In this part, the related techniques of GCC compilation are studied, and the process of GCC compilation is deeply analyzed. The emphasis is on the generation process from intermediate representation of Gimple Tree to RTL, as well as the RTL optimization and processing process, and the assembly code output process. Secondly, this article starts with simple assignment expressions. Arithmetic and logic operation expressions, special expressions and function calls and other instruction types of the processing process to describe the specific implementation of the tasklet. Again. The fault injection experiment is carried out on our micro-thread fault detection scheme by using the fault injection platform, and the experimental results are analyzed, which can be seen from the experimental results. The compile-based micro-thread fault detection technique presented in this paper has a good performance in fault-tolerant performance, and the cost of sacrificing time and space is within a reasonable range.
【學(xué)位授予單位】:哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2012
【分類號(hào)】:TP302.8

【參考文獻(xiàn)】

相關(guān)期刊論文 前5條

1 王長河;單粒子效應(yīng)對(duì)衛(wèi)星空間運(yùn)行可靠性影響[J];半導(dǎo)體情報(bào);1998年01期

2 楊學(xué)軍;高瓏;;空間探測(cè)中基于COTS部件的軟件容錯(cuò)技術(shù)[J];計(jì)算機(jī)工程與科學(xué);2007年08期

3 徐建軍;譚慶平;熊蔭喬;譚蘭芳;李建立;;面向瞬態(tài)故障的軟件容錯(cuò)技術(shù)[J];計(jì)算機(jī)工程與科學(xué);2011年11期

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