本文關(guān)鍵詞： 中斷系統(tǒng) 數(shù)字信號(hào)處理器 中斷向量表 中斷優(yōu)先級(jí) 外圍設(shè)備控制處理器　出處：《江南大學(xué)》2013年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著我國(guó)電子信息產(chǎn)業(yè)的發(fā)展,數(shù)字信號(hào)處理器(DSP)在軍用和民用領(lǐng)域取得了越來(lái)越廣泛的應(yīng)用。巨大的市場(chǎng)壓力使得DSP朝著高性能、低功耗的方向邁進(jìn)。由于DSP內(nèi)核和外設(shè)的通訊是依靠中斷系統(tǒng)來(lái)完成的,因此中斷系統(tǒng)的優(yōu)劣己經(jīng)成為了影響DSP性能的重要因素之一 本論文在分析傳統(tǒng)中斷系統(tǒng)的基本結(jié)構(gòu)及工作原理的基礎(chǔ)上,設(shè)計(jì)并實(shí)現(xiàn)了一種高性能DSP中斷系統(tǒng)。此中斷系統(tǒng)擁有兩個(gè)中斷處理器,最大支持255個(gè)優(yōu)先級(jí),其中斷向量表的中斷服務(wù)例程可跨越且中斷優(yōu)先級(jí)可分組。在實(shí)際應(yīng)用中優(yōu)先級(jí)和仲裁時(shí)間可靈活設(shè)置,使得中斷源被合理分配,減少了DSP在中斷處理上的消耗,提高了DSP內(nèi)核的運(yùn)算效率。 本論文設(shè)計(jì)的中斷系統(tǒng)由服務(wù)請(qǐng)求商、服務(wù)請(qǐng)求節(jié)點(diǎn)(SRN)、中斷控制單元(ICU和PICU)、兩根中斷仲裁總線和中斷服務(wù)提供商五部分組成。本中斷系統(tǒng)的兩個(gè)中斷服務(wù)提供商分別為DSP和外圍設(shè)備控制處理器(PCP),它們共同處理服務(wù)請(qǐng)求商發(fā)出的中斷服務(wù)請(qǐng)求；服務(wù)請(qǐng)求商一般指需要申請(qǐng)中斷的外設(shè)(包括DSP和PCP本身)；外設(shè)通過(guò)與自身相連的一個(gè)或多個(gè)服務(wù)請(qǐng)求節(jié)點(diǎn)向中斷服務(wù)提供商申請(qǐng)中斷服務(wù)請(qǐng)求,服務(wù)請(qǐng)求節(jié)點(diǎn)通過(guò)可選的DSP中斷仲裁總線或者PCP中斷仲裁總線將中斷服務(wù)請(qǐng)求發(fā)送到對(duì)應(yīng)的中斷控制單元(ICU或PICU)；中斷控制單元負(fù)責(zé)仲裁收到的服務(wù)請(qǐng)求,確定擁有最高優(yōu)先級(jí)的中斷服務(wù)請(qǐng)求,并向?qū)?yīng)的DSP或者PCP生成中斷請(qǐng)求；最后DSP或者PCP響應(yīng)并處理中斷。 利用硬件描述語(yǔ)言VHDL對(duì)中斷系統(tǒng)進(jìn)行了RTL級(jí)的描述,采用SYNOPSYS公司的仿真軟件VCS在系統(tǒng)層次上對(duì)各種不同的中斷事件進(jìn)行了時(shí)序驗(yàn)證。結(jié)果表明,中斷系統(tǒng)的設(shè)計(jì)達(dá)到了預(yù)期要求；在高頻DSP系統(tǒng)中,在仲裁周期上可節(jié)省2到6個(gè)時(shí)鐘周期,提高了系統(tǒng)效率。此中斷系統(tǒng)己運(yùn)用于一款DSP芯片中并成功投入市場(chǎng)。
[Abstract]:With the development of electronic information industry in China, digital signal processor (DSP) has been more and more widely used in military and civilian fields. Since the communication between DSP kernel and peripheral devices depends on interrupt system, the quality of interrupt system has become one of the important factors that affect the performance of DSP. On the basis of analyzing the basic structure and working principle of the traditional interrupt system, this paper designs and implements a high-performance DSP interrupt system, which has two interrupt processors. The maximum support is 255 priority, in which interrupt service routine can cross and interrupt priority can be grouped. In practical application, priority and arbitration time can be set flexibly, so interrupt source can be allocated reasonably. The consumption of DSP in interrupt processing is reduced, and the efficiency of DSP kernel is improved. The interrupt system designed in this paper is composed of service requester, service request node, interrupt control unit, ICU and PICU). The two interrupt arbitration bus and the interrupt service provider are composed of five parts. The two interrupt service providers of the interrupt system are DSP and peripheral equipment control processor (DSP). They jointly process service interruption requests from service requesters; Service requesters generally refer to peripherals (including DSP and PCP themselves) that need to apply for interruptions; The peripheral applies to an interrupt service provider for an interrupt service request through one or more service request nodes connected to itself. The service request node sends the interrupt service request to the corresponding interrupt control unit (ICICU) or PICUU via the optional DSP interrupt arbitration bus or the PCP interrupt arbitration bus. The interrupt control unit is responsible for arbitrating the received service request, determining the interrupt service request with the highest priority, and generating the interrupt request to the corresponding DSP or PCP. Finally, DSP or PCP responds and handles interruptions. The hardware description language VHDL is used to describe the interrupt system at RTL level. The simulation software VCS of SYNOPSYS Company is used to verify the timing of different interrupt events at the system level. The results show that the design of the interrupt system meets the expected requirements. In high frequency DSP system, two to six clock cycles can be saved in the arbitration cycle, and the system efficiency is improved. The interrupt system has been used in a DSP chip and successfully put into the market.
【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 馬學(xué)軍,陳息坤,康勇;一種新的基于DSP的高精度UPS鎖相技術(shù)[J];電工電能新技術(shù);2005年04期

2 陳云窗,侯朝楨,湯霞清;TMS320C31和80C196雙CPU構(gòu)成的高速實(shí)時(shí)控制系統(tǒng)[J];電子技術(shù)應(yīng)用;2001年08期

3 涂軍;陳意翔;吳安清;楊凡;;一種基于DSP技術(shù)的動(dòng)態(tài)圖像高速采集系統(tǒng)的設(shè)計(jì)[J];湖北工業(yè)大學(xué)學(xué)報(bào);2006年02期

4 杭強(qiáng)偉,陸菊康,譚成翔,王玨,朱肇中;基于DSP的VPN安全網(wǎng)關(guān)的設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)應(yīng)用;2004年03期

5 劉月吉;張盛兵;黃嵩人;;一種DSP的快速上下文切換機(jī)制[J];計(jì)算機(jī)應(yīng)用研究;2012年01期

6 王挺;丁志剛;閻夢(mèng)天;宗宇偉;;實(shí)時(shí)操作系統(tǒng)內(nèi)核時(shí)間參數(shù)的測(cè)量[J];計(jì)算機(jī)應(yīng)用與軟件;2009年07期

7 王德東;陶俊勇;蔣瑜;吳艷;;基于DSP的定時(shí)器在模數(shù)和數(shù)模轉(zhuǎn)換中的應(yīng)用[J];計(jì)算機(jī)測(cè)量與控制;2008年06期

8 劉冠志;林輝;;飛機(jī)全電剎車(chē)驅(qū)動(dòng)器設(shè)計(jì)與關(guān)鍵技術(shù)研究[J];計(jì)算機(jī)測(cè)量與控制;2010年02期

9 魏建磊;王茹;;DSP芯片中雙通道DMA的研究與設(shè)計(jì)[J];計(jì)算機(jī)技術(shù)與發(fā)展;2008年03期

10 柳愛(ài)美,成曉明,羅安,孫志國(guó);DSP與上位機(jī)之間數(shù)據(jù)通信的研究與應(yīng)用[J];微計(jì)算機(jī)信息;2002年08期

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