發(fā)布時(shí)間：2018-01-28 17:37

  本文關(guān)鍵詞： SRAM 存儲(chǔ)器測(cè)試 動(dòng)態(tài)故障 靜態(tài)故障 TSMC180nm工藝 阻抗性開路　出處：《南京航空航天大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著嵌入式存儲(chǔ)器在片上系統(tǒng)(SoC)中的使用越來(lái)越廣泛，嵌入式存儲(chǔ)器測(cè)試在工業(yè)界和學(xué)術(shù)界受到了廣泛關(guān)注。隨著存儲(chǔ)器工藝尺寸的減小，為了獲得高存儲(chǔ)密度和快速的存取速度，SRAM可能會(huì)在制造時(shí)出現(xiàn)一些新的缺陷。由于嵌入式存儲(chǔ)器通常比較復(fù)雜，因此故障的建模和測(cè)試成為了一項(xiàng)比較困難的任務(wù)。經(jīng)典的存儲(chǔ)器測(cè)試算法只適用于靜態(tài)故障，而不足以測(cè)試超深亞微米(Very Deep Sub-Micron, VDSM)技術(shù)下出現(xiàn)的新型故障，這類新型故障被稱為動(dòng)態(tài)故障。因此，研究SRAM的動(dòng)態(tài)故障具有重要的理論意義與實(shí)用價(jià)值。 本文以SRAM的動(dòng)態(tài)故障測(cè)試為研究?jī)?nèi)容，主要研究?jī)?nèi)容如下： (1)基于六晶體管構(gòu)建簡(jiǎn)化的SRAM電路及其參數(shù)的選取。為縮短仿真時(shí)間，構(gòu)建了一種簡(jiǎn)化的SRAM電路，包括預(yù)沖電路和寫驅(qū)動(dòng)，并通過(guò)仿真證實(shí)了此簡(jiǎn)化電路具有正確的讀、寫以及保持?jǐn)?shù)據(jù)的功能。鑒于本文仿真在TSMC180nm工藝下進(jìn)行，且結(jié)合存儲(chǔ)單元的W/L比例限制，最終決定選取了各晶體管的尺寸。 (2) SRAM存儲(chǔ)單元的阻抗性開路故障研究。首先介紹了存儲(chǔ)單元并對(duì)其存在的故障進(jìn)行了分析研究，重點(diǎn)研究了動(dòng)態(tài)讀破壞故障(dRDF)產(chǎn)生的原因及其測(cè)試算法，通過(guò)仿真實(shí)驗(yàn)得出了讀操作的次數(shù)M、植入故障的阻值和讀操作周期之間的聯(lián)系。然后對(duì)靜態(tài)故障也進(jìn)行了仿真實(shí)驗(yàn)，并比較了靜態(tài)故障與動(dòng)態(tài)故障之間的差異。 (3) SRAM預(yù)沖電路的阻抗性開路故障研究。首先介紹了預(yù)充電路并對(duì)其存在的故障進(jìn)行了分析研究，重點(diǎn)研究了未修復(fù)寫故障(URWF)和未修復(fù)讀故障(URRF)產(chǎn)生的原因及對(duì)應(yīng)的測(cè)試算法，并通過(guò)仿真驗(yàn)證了算法的有效性，且發(fā)現(xiàn)URWF的測(cè)試效率要比URRF的測(cè)試效率高。 以上所有仿真均采用TSMC180nm工藝，且在動(dòng)態(tài)故障研究中首次采用180nm工藝，最后通過(guò)Hspice電路仿真軟件進(jìn)行仿真、驗(yàn)證。
[Abstract]:With the increasing use of embedded memory in SoC (system on Chip), embedded memory testing has attracted wide attention in industry and academia. In order to obtain high storage density and fast access speed, SRAM may have some new defects in manufacturing, because embedded memory is usually more complex. Therefore, fault modeling and testing has become a difficult task. The classical memory test algorithm is only suitable for static fault. But not enough to test the new faults that occur under the very submicron Deep Sub-micron (VDSM) technology, which are called dynamic failures. It is of great theoretical significance and practical value to study the dynamic faults of SRAM. In this paper, the dynamic fault test of SRAM is taken as the research content, the main research contents are as follows: In order to shorten the simulation time, a simplified SRAM circuit is constructed, including pre-punching circuit and write driver. It is proved by simulation that the simplified circuit has the function of reading, writing and keeping data correctly. In view of the fact that the simulation in this paper is carried out under the TSMC180nm technology, and combined with the W / L ratio limitation of the memory cell. The final decision is to choose the size of each transistor. Second, the research of impedance open circuit fault of SRAM memory cell. Firstly, the memory cell is introduced and its faults are analyzed. The cause of dynamic read failure fault and its testing algorithm are studied. The times of read operation M are obtained by simulation experiment. Then the static fault is simulated and the difference between the static fault and the dynamic fault is compared. First, the precharging circuit is introduced and the existing faults are analyzed. The causes of unrepaired write fault (URWFF) and unrepaired read fault (URRFF) and the corresponding test algorithms are studied, and the validity of the algorithm is verified by simulation. The test efficiency of URWF is higher than that of URRF. All of the above simulations are based on TSMC180nm technology, and 180nm process is used for the first time in the dynamic fault research. Finally, the simulation software of Hspice circuit is used to verify the simulation.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333

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本文編號(hào)：1471127