本文關(guān)鍵詞： PCIe 高速 數(shù)據(jù)傳輸 實時操作系統(tǒng)　出處：《浙江大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：PCIe總線具有高帶寬以及良好的擴展性,已被廣泛用于計算機與各種外設(shè)的互連,但其在嵌入式領(lǐng)域還并未獲得廣泛應(yīng)用。針對當(dāng)今大數(shù)據(jù)量的高速傳輸需求,本文探討了基于PCIe總線的高速數(shù)據(jù)傳輸技術(shù),并設(shè)計與實現(xiàn)了一個基于PCIe總線以及實時操作系統(tǒng)的嵌入式高速數(shù)據(jù)傳輸系統(tǒng)。本文設(shè)計的高速數(shù)據(jù)傳輸系統(tǒng)具有較高的傳輸速率,支持雙向傳輸,可根據(jù)傳輸數(shù)據(jù)量的大小選擇最優(yōu)底層傳輸方式,主控端可對傳輸系統(tǒng)進行全面控制。本文首先提出了高速數(shù)據(jù)傳輸系統(tǒng)的總體設(shè)計方案,包括總體硬件方案、軟件方案以及數(shù)據(jù)通路方案。然后著重設(shè)計并實現(xiàn)了傳輸系統(tǒng)軟件,根據(jù)高速數(shù)據(jù)傳輸系統(tǒng)的功能需求,將其軟件分為底層驅(qū)動以及上層應(yīng)用兩部分。在底層驅(qū)動部分重點設(shè)計并完成了 PCIeEP端初始化、與PCIeRC的通信協(xié)議、底層傳輸方式、以及與上層應(yīng)用的交互方式等。在上層應(yīng)用部分主要設(shè)計并實現(xiàn)了傳輸功能模塊以及FPGA配置模塊。最后搭建測試平臺對系統(tǒng)進行測試驗證,結(jié)果表明驅(qū)動以及應(yīng)用程序功能正常,高速數(shù)據(jù)傳輸系統(tǒng)上行以及下行傳輸速率可達1637MB/s左右,達到了所用PCIe鏈路理論傳輸速度的89.1%,達到所預(yù)期的傳輸速率,滿足高速數(shù)據(jù)傳輸需求。
[Abstract]:PCIe bus with high bandwidth and good scalability has been widely used in computer interconnection with various peripherals. However, it has not been widely used in the embedded field. In order to meet the demand of high-speed data transmission, this paper discusses the high-speed data transmission technology based on PCIe bus. An embedded high-speed data transmission system based on PCIe bus and real time operating system is designed and implemented. The high speed data transmission system designed in this paper has high transmission rate and supports two-way transmission. According to the size of the transmission data, the main control terminal can control the transmission system. Firstly, the overall design scheme of the high-speed data transmission system, including the overall hardware scheme, is proposed. Software scheme and data path scheme. Then the design and implementation of the transmission system software, according to the functional requirements of high-speed data transmission system. The software is divided into two parts: the bottom driver and the upper application. In the bottom driver part, the initialization of the PCIeEP terminal, the communication protocol with the PCIeRC, and the underlying transmission mode are designed and completed. In the upper application part, the transmission function module and the FPGA configuration module are designed and implemented. Finally, the test platform is built to test and verify the system. The results show that the functions of the driver and the application are normal, and the uplink and downlink transmission rate of the high-speed data transmission system can reach about 1637MB / s. The PCIe theoretical transmission speed is 89.1%, the expected transmission rate is achieved, and the high speed data transmission requirement is satisfied.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP316.2;TP336

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本文編號：1442230