本文關(guān)鍵詞：基于FPGA的32位五級(jí)流水線CPU的研究與設(shè)計(jì)　出處：《河北工業(yè)大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： FPGA 流水線 CPU Verilog HDL

【摘要】：目前，國(guó)內(nèi)大部分高校的計(jì)算機(jī)組成實(shí)驗(yàn)平臺(tái)是純硬件化的，內(nèi)部結(jié)構(gòu)固定，靈活性差，不利于學(xué)生自主創(chuàng)新，大大降低了教學(xué)質(zhì)量。FPGA技術(shù)提供了一個(gè)靈活的設(shè)計(jì)平臺(tái)，本論文采用FPGA技術(shù)，設(shè)計(jì)了32位五級(jí)流水線CPU，可應(yīng)用于計(jì)算機(jī)組成實(shí)驗(yàn)課程，有助于提高教學(xué)質(zhì)量。 論文根據(jù)實(shí)際需要，結(jié)合理論研究，提出了基于FPGA的五級(jí)流水線CPU的總體結(jié)構(gòu)模型，利用DE2開發(fā)平臺(tái)完成了32位五級(jí)流水線CPU的設(shè)計(jì)過程，實(shí)現(xiàn)了取指IF、指令譯碼ID、指令執(zhí)行EXE、存儲(chǔ)MEM和結(jié)果寫回WB五個(gè)周期的功能設(shè)計(jì)，并專門設(shè)計(jì)了流水線演示系統(tǒng)，通過對(duì)系統(tǒng)演示效果的分析，驗(yàn)證了CPU設(shè)計(jì)的合理性。 論文采用Verilog HDL語言，完成了流水線CPU五個(gè)周期的設(shè)計(jì)。取指周期設(shè)計(jì)了PC寄存器和指令存儲(chǔ)器，實(shí)現(xiàn)了取指令功能；譯碼周期設(shè)計(jì)了控制器CU、寄存器堆等部件，完成了20條指令的譯碼功能；指令執(zhí)行周期主要對(duì)運(yùn)算器ALU的設(shè)計(jì)，實(shí)現(xiàn)了對(duì)數(shù)據(jù)的運(yùn)算操作；存儲(chǔ)周期完成了數(shù)據(jù)存儲(chǔ)器的設(shè)計(jì)，用于存儲(chǔ)周期的讀寫操作；結(jié)果寫回周期，通過設(shè)計(jì)多路器，實(shí)現(xiàn)將正確的結(jié)果寫回到目的寄存器中。流水線的設(shè)計(jì)，必然帶來相關(guān)問題，含有數(shù)據(jù)相關(guān)、控制相關(guān)和結(jié)構(gòu)相關(guān)。論文重點(diǎn)對(duì)前兩種相關(guān)進(jìn)行了研究與處理，，設(shè)計(jì)了內(nèi)部前推方法和暫停流水方法相結(jié)合的策略，解決了流水線數(shù)據(jù)相關(guān)問題，采用延遲轉(zhuǎn)移法，解決了流水線控制相關(guān)問題。論文設(shè)計(jì)了流水線演示系統(tǒng)，實(shí)現(xiàn)了流水線演示及效果分析的功能。 最后，編寫了測(cè)試程序，在FPGA平臺(tái)上對(duì)流水線CPU進(jìn)行了功能驗(yàn)證，并分析了流水效果，CPU運(yùn)行正常，功能完備，取得了預(yù)期的結(jié)果。
[Abstract]:At present, most of the computer composition of the experimental platform in colleges and universities is pure hardware, the internal structure is fixed, flexibility is poor, which is not conducive to independent innovation of students. Greatly reduce the quality of teaching. FPGA technology provides a flexible design platform, this paper uses FPGA technology, designed 32-bit five-level pipeline CPU, can be used in the computer to form an experimental course. It helps to improve the quality of teaching. According to the actual needs, combined with the theoretical research, this paper puts forward the overall structure model of five-level pipeline CPU based on FPGA. The design process of 32-bit five-level pipeline CPU is completed by using DE2 development platform. The functional design of storing MEM and writing the result back to WB is presented, and the pipeline demonstration system is specially designed. The rationality of CPU design is verified by analyzing the effect of system demonstration. In this paper, the five cycles of pipeline CPU are designed by using Verilog HDL language, and the PC register and instruction memory are designed, and the instruction fetching function is realized. The decoding cycle includes the design of the controller CUand the register file and the decoding function of 20 instructions. The instruction execution cycle is mainly about the design of ALU, and the operation of data is realized. The storage cycle completes the design of the data storage, which is used to read and write the storage cycle. By designing multiplexer, the correct result can be written back to the destination register. Pipeline's design will inevitably bring related problems, including data correlation. Control correlation and structural correlation. This paper focuses on the first two kinds of correlation research and processing, design the internal forward push method and pause income method combined strategy, solve pipeline data related problems. The paper designs pipeline demonstration system and realizes the function of pipeline demonstration and effect analysis. Finally, a test program is written to verify the function of pipeline CPU on FPGA platform, and the result of income is analyzed.
【學(xué)位授予單位】：河北工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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