本文關(guān)鍵詞：基于FPGA的8位嵌入式CPU設(shè)計(jì)　出處：《杭州電子科技大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： CPU FPGA RISC指令集 模塊化

【摘要】：隨著網(wǎng)絡(luò)時(shí)代的到來,網(wǎng)絡(luò)通信、信息安全和信息家電產(chǎn)品將越來越普及,而CPU正是所有這些信息產(chǎn)品中必不可少的部件。目前,擁有自主知識(shí)產(chǎn)權(quán)的CPU對(duì)國家的軍事、經(jīng)濟(jì)及安全具有深遠(yuǎn)的意義�；谶@個(gè)原因,在深入了解了CPU的結(jié)構(gòu)、工作原理及設(shè)計(jì)方法后,本文以FPGA為開發(fā)平臺(tái),采用Quartus(?)Ⅱ軟件所支持的原理圖設(shè)計(jì)方式,從基礎(chǔ)邏輯電路設(shè)計(jì)開始,逐步完成嵌入式CPU的設(shè)計(jì)。 主要工作內(nèi)容包括以下幾個(gè)主要方面： (1)為了設(shè)計(jì)性能良好的嵌入式CPU,在深入了解分析經(jīng)典CPU基本結(jié)構(gòu),經(jīng)典CPU指令集的基礎(chǔ)上,選取或自己擬定一套切實(shí)可行的指令集。在本次設(shè)計(jì)中,以RISC指令集中的ARM、MIPS經(jīng)典指令為參考,擬定了一套R(shí)ISC指令集。RISC指令集是高性能CPU的發(fā)展方向。它與傳統(tǒng)的CISC(復(fù)雜指令集)相對(duì)。相比而言,RISC的指令格式統(tǒng)一,種類比較少,尋址方式也比復(fù)雜指令集少。 (2)在擬定好CPU指令集的基礎(chǔ)上,使用Quartus(?)Ⅱ軟件工具,通過邏輯圖輸入方法設(shè)計(jì)可實(shí)現(xiàn)這套指令集的CPU的邏輯電路。使用模塊化設(shè)計(jì)思想,從CPU的局部功能到總體結(jié)構(gòu)自底向上設(shè)計(jì)。CPU是一個(gè)復(fù)雜的數(shù)字電路,其主要電路為控制器,運(yùn)算器及各種內(nèi)部寄存器。在設(shè)計(jì)好CPU內(nèi)部各個(gè)受控功能模塊后,最后由控制器安排CPU的工作時(shí)序。需要設(shè)計(jì)的詳細(xì)電路有：算術(shù)邏輯單元(ALU)、移位模塊、譯碼模塊、特殊寄存器模塊、程序計(jì)數(shù)器(PC)、程序狀態(tài)字寄存器(PSW)、10模塊、時(shí)鐘信號(hào)產(chǎn)生模塊等。 (3)為了驗(yàn)證所設(shè)計(jì)的CPU邏輯電路的正確性,利用Quartus(?)Ⅱ軟件工具對(duì)各個(gè)邏輯電路進(jìn)行仿真。從基本邏輯電路仿真,小模塊仿真到大模塊仿真,最后是整個(gè)CPU電路的仿真。使用逐級(jí)仿真實(shí)現(xiàn)對(duì)所設(shè)計(jì)的CPU進(jìn)行功能模擬,從而確保CPU功能的正確性。 (4)為了方便演示這款CPU的功能,在FPGA中構(gòu)建一個(gè)額外的RAM代替原來存放指令的外部ROM,并搭建一個(gè)調(diào)試器。此調(diào)試器旨在方便各指令代碼的寫入,方便驗(yàn)證各指令的執(zhí)行結(jié)果。 (5)本文旨在給出基于FPGA的嵌入式CPU的設(shè)計(jì)方案,包括軟件平臺(tái)、設(shè)計(jì)流程、各功能模塊、測試波形圖等。給出一種使用FPGA設(shè)計(jì)CPU的方法。由于CPU是一個(gè)復(fù)雜的數(shù)字電路,為了在較短時(shí)間里完成CPU的設(shè)計(jì),給出詳細(xì)的設(shè)計(jì)流程,在此設(shè)計(jì)了一款8位嵌入式CPU。
[Abstract]:With the advent of network era , network communication , information security and information household appliance products will become more and more popular , and CPU is the essential part of all these information products . At present , the CPU with independent intellectual property has profound significance to the military , economic and security of the country . Based on this reason , based on FPGA as the development platform , the design of embedded CPU is gradually completed by using the schematic design mode supported by Quartus ( ? ) II software . The main tasks include the following major aspects : ( 1 ) In order to design an embedded CPU with good performance , a set of practical instruction sets is selected or developed on the basis of an in - depth understanding of the basic structure of the classic CPU and a classic CPU instruction set . In this design , a RISC instruction set is developed based on ARM and mips instruction set in RISC instruction set . The RISC instruction set is the development direction of high performance CPU . Compared with the traditional CISC ( complex instruction set ) , the instruction format of RISC is uniform , the type is less , and the addressing mode is less than the complex instruction set . ( 2 ) By using Quartus ( ? ) 鈪，

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