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  本文關(guān)鍵詞：基于FPGA的多片NAND FLASH并行存儲控制器的設(shè)計與實現(xiàn)　出處：《山東大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： FPGA實現(xiàn) 多片并行 NAND FLASH控制器 ECC校驗 FSM

【摘要】：隨著嵌入式系統(tǒng)的發(fā)展,對數(shù)據(jù)存儲量的要求正在快速增長。FLASH具有速度快、密度大、非易失性及可擦除性等特點,正在得到越來越廣泛的應(yīng)用。FLASH主要有NOR和NAND兩種,而NAND FLASH具有更小的體積、更快的寫入和擦除速度、更多的可擦寫次數(shù)以及更低廉的每比特價格,成為了大量數(shù)據(jù)存儲的理想器件。 基于閃存的固態(tài)硬盤,采用FLASH芯片作為存儲介質(zhì),這也是我們通常所說的SSD。與傳統(tǒng)的硬盤相比,它由固態(tài)電子存儲芯片陣列制成,內(nèi)部沒有機(jī)械裝置,因此,SSD具有更快的讀取速度,沒有噪音,發(fā)熱量低,不會發(fā)生機(jī)械故障,工作溫度范圍大,體積小,重量輕,抗震動的優(yōu)點。雖然有容量小,成本高,數(shù)據(jù)難以恢復(fù)等缺點,但是,隨著技術(shù)的不斷發(fā)展進(jìn)步,固態(tài)硬盤的技術(shù)發(fā)展也將更加完善,固態(tài)硬盤也將得到更加廣泛的應(yīng)用。 NAND FLASH的控制邏輯復(fù)雜,數(shù)據(jù)、地址采用同一總線,實現(xiàn)串行讀取,隨機(jī)讀取速度慢且不能按字節(jié)隨機(jī)編程。因此,本文探討了基于Xilinx Spartan-3E的多片NAND FLASH并行存儲控制器的設(shè)計方案,設(shè)計實現(xiàn)了類SRAM接口,處理器能夠按照SRAM接口標(biāo)準(zhǔn)對NAND FLASH進(jìn)行操作而不需要考慮NAND FLASH的接口規(guī)范,方便了NAND FLASH應(yīng)用的擴(kuò)展。 基于FPGA的多片NAND FLASH并行存儲控制器,實現(xiàn)了SRAM接口和NAND FLASH接口的轉(zhuǎn)換,將復(fù)雜不通用的NAND接口轉(zhuǎn)化為了簡單通用的SRAM接口,能夠控制多片NAND FLASH的讀寫等操作；實現(xiàn)ECC校驗功能,對寫入和讀出的數(shù)據(jù)進(jìn)行校驗操作,提高處理效率；控制多片NAND FLASH芯片,擴(kuò)大了容量,提高了并行處理能力,便于實現(xiàn)SSD。 綜上所述,基于FPGA的多片NAND FLASH并行存儲控制器的設(shè)計實現(xiàn),不僅具有理論研究的價值,在SSD設(shè)計實現(xiàn)方面有實際的利用價值。
[Abstract]:With the development of embedded system, the data storage requirements are the rapid growth of.FLASH high speed, high density, non-volatile and erase characteristics and so on, are getting more and more NOR and NAND two.FLASH mainly used more widely, while NAND FLASH has a smaller volume, faster write and erase speed, more erasing times and more lower price per bit, become the ideal device for large data storage.
The flash based, using FLASH chip as the storage medium, compared to this is what we usually refer to the SSD. and the traditional hard disk, which is composed of solid state electronic memory chip arrays made no mechanical devices, so internal, SSD has faster read speed, no noise, low heat, no mechanical failure, working temperature large range, small size, light weight, anti vibration advantages. Although there is a small capacity, high cost, difficult to restore data shortcomings, however, with the development of technology, technology development of solid state disk will also be more perfect, SSD will be more widely used.
NAND FLASH complex control logic, data address using the same bus, serial read, random read speed is slow and can not be random byte programming. Therefore, this paper discusses the design scheme of Xilinx Spartan-3E multi NAND FLASH parallel storage controller based on the design and implementation of the SRAM interface, the processor can according to SRAM interface standard NAND FLASH to operate without considering the interface specification of NAND FLASH, NAND FLASH for extension of the application.
FPGA multi NAND parallel storage controller based on FLASH, realize the conversion of SRAM interface and NAND FLASH interface, NAND interface complex general SRAM interface into simple and general, can control the multi chip NAND FLASH read and write operations; realize ECC checksum function, check the operation of the data read and write and improve the processing efficiency; control of multi chip NAND FLASH chip, to expand capacity, improve the parallel processing ability to implement SSD.
To sum up, the design and implementation of multi chip NAND FLASH parallel memory controller based on FPGA not only has the value of theoretical research, but also has practical value in SSD design and implementation.

【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333;TP273

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本文編號：1393999