本文關(guān)鍵詞：RISC處理器整數(shù)運(yùn)算和控制單元的研究與設(shè)計(jì)　出處：《華北電力大學(xué)》2012年碩士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： RISC 整數(shù)控制單元 整數(shù)運(yùn)算單元 指令流水 仿真

【摘要】：隨著信息技術(shù)的發(fā)展,作為嵌入式系統(tǒng)的核心,微處理器以其靈活,功能強(qiáng)大等優(yōu)勢(shì),已廣泛應(yīng)用在信息技術(shù)的各個(gè)領(lǐng)域。無(wú)論是家電產(chǎn)品多媒體和數(shù)字信號(hào)處理領(lǐng)域,還是衛(wèi)星發(fā)射導(dǎo)彈制導(dǎo)都離不開(kāi)微處理器。其中RISC(精簡(jiǎn)指令集計(jì)算機(jī))因?yàn)楫a(chǎn)生的機(jī)器碼更有效、更密集,使得編碼器很容易實(shí)現(xiàn)其密度接近于機(jī)器能力的代碼,其性能價(jià)格比超過(guò)了傳統(tǒng)的CISC,速度也比CISC快,且硬件結(jié)構(gòu)功能分布清楚,工藝技術(shù)先進(jìn)等優(yōu)點(diǎn),越來(lái)越受到人們的重視和使用。論文在對(duì)嵌入式微處理器通用結(jié)構(gòu)研究的基礎(chǔ)上,參考SPARC V8指令系統(tǒng),實(shí)現(xiàn)了微處理器整數(shù)運(yùn)算和控制單元的設(shè)計(jì)。 本課題的內(nèi)容是設(shè)計(jì)RISC處理器的整數(shù)運(yùn)算和控制單元。該單元是微處理器的主要組成部分,其主要作用是執(zhí)行所有的整數(shù)運(yùn)算指令和控制指令。整數(shù)運(yùn)算能力是CPU中重要的性能指標(biāo)。整數(shù)運(yùn)算和控制單元的設(shè)計(jì)研究對(duì)高性能的處理器設(shè)計(jì)有著重要的意義。本單元兼容SPARC V8標(biāo)準(zhǔn)的指令級(jí)；采用5級(jí)指令流水線實(shí)現(xiàn)；支持8個(gè)寄存器窗口；可配置的乘法器；基2的不恢復(fù)除法器；支持與IU串行的浮點(diǎn)處理器單元和協(xié)處理器等； 本文詳細(xì)闡述了整數(shù)控制單元五級(jí)指令流水的實(shí)現(xiàn)方式,同時(shí)對(duì)整數(shù)運(yùn)算單元中加法器,乘法器,除法器和整數(shù)控制部件的設(shè)計(jì)分別做了詳盡的闡述。作者使用VHDL語(yǔ)言對(duì)整數(shù)控制與運(yùn)算單元進(jìn)行RTL描述,在完成設(shè)計(jì)的功能仿真后,還對(duì)設(shè)計(jì)中的乘法器,除法器和控制部件在XILINX公司的Virtex-5系列芯片進(jìn)行了FPGA驗(yàn)證,整數(shù)運(yùn)算和控制單元頻率達(dá)到184MHz,驗(yàn)證結(jié)果表明我們所設(shè)計(jì)的模塊功能和性能都符合預(yù)期。
[Abstract]:With the development of information technology, as the core of the embedded system, the microprocessor with its powerful and flexible, and other advantages, has been widely used in various fields of information technology. Both the field of multimedia and digital signal processing appliances, or satellite launch missile guidance all cannot do without the microprocessor. The RISC (reduced instruction set computer) because the machine code is more effective, more intensive, the encoder is easy to implement the density close to the machine capacity of the code, the performance price ratio than the traditional CISC, the speed is faster than CISC, and the hardware structure and function clear, advanced technology and other advantages, more and more people's attention and use in the paper. On the basis of the general structure of embedded microprocessor, SPARC V8 instruction system, realizes the design of microprocessor integer arithmetic and control unit.
The content of this paper is the integer arithmetic and control unit design of RISC processor. The unit is mainly composed of a microprocessor, its main function is to execute integer instructions and the control instructions. All integer arithmetic ability is an important performance index. CPU plays an important role in design of integer arithmetic and control unit processor the design of high performance. This unit is compatible with SPARC instruction level V8 standard; the 5 stage instruction pipeline implementation; support 8 register windows; configurable multiplier; base 2 does not restore divider; floating point processor unit and support IU serial and coprocessor etc.;
This paper describes the realization of the control unit five level integer pipelining, and the integer unit in the adder, multiplier, divider design and integer control parts respectively in detail. The author uses the VHDL language to describe the RTL integer control and operation unit, in complete function simulation design, but also to design the multiplier, Virtex-5 series chip in XILINX divider and control components of the FPGA verification, integer arithmetic and control unit frequency reaches 184MHz, the verification results show that the module we designed can work and performance are consistent with expectations.

【學(xué)位授予單位】：華北電力大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前7條

1 湯曉慧,楊軍,吳艷,吳建輝;基于Booth算法的32×32乘法器IP核設(shè)計(jì)[J];電子器件;2005年01期

2 朱一杰,張曦,俞軍;雙字節(jié)Booth乘法器的優(yōu)化設(shè)計(jì)[J];復(fù)旦學(xué)報(bào)(自然科學(xué)版);2005年01期

3 金美華;宋萬(wàn)杰;吳順君;;FPGA中浮點(diǎn)乘法器的實(shí)現(xiàn)[J];火控雷達(dá)技術(shù);2008年01期

4 夏宏,吳克河,李占才;浮點(diǎn)加法器電路設(shè)計(jì)算法的研究[J];計(jì)算機(jī)工程與應(yīng)用;2001年13期

5 邵磊;李昆;張樹(shù)丹;于宗光;徐睿;;基于改進(jìn)4-2壓縮結(jié)構(gòu)的32位浮點(diǎn)乘法器設(shè)計(jì)[J];微計(jì)算機(jī)信息;2007年09期

6 葛亮,唐志敏;一種支持無(wú)符號(hào)數(shù)的流水線乘法器[J];微電子學(xué)與計(jì)算機(jī);2002年10期

7 王曉莉;黃偉;王典洪;;高速流水線浮點(diǎn)加法器的FPGA實(shí)現(xiàn)[J];電子元器件應(yīng)用;2009年04期

相關(guān)博士學(xué)位論文 前1條

1 夏軍;32位RISC微處理器設(shè)計(jì)研究[D];華中科技大學(xué);2004年

相關(guān)碩士學(xué)位論文 前2條

1 王重陽(yáng);單、雙、擴(kuò)展精度自適應(yīng)浮點(diǎn)乘、除和開(kāi)方運(yùn)算單元的實(shí)現(xiàn)[D];華北電力大學(xué)（北京）;2011年

2 朱國(guó)勇;可重組整數(shù)單元的研究與設(shè)計(jì)[D];華北電力大學(xué)（北京）;2008年

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