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基于FPGA的存儲控制器及相關(guān)系統(tǒng)設(shè)計技術(shù)研究

發(fā)布時間:2018-01-05 02:34

  本文關(guān)鍵詞:基于FPGA的存儲控制器及相關(guān)系統(tǒng)設(shè)計技術(shù)研究 出處:《浙江大學(xué)》2017年碩士論文 論文類型:學(xué)位論文


  更多相關(guān)文章: FPGA NVMe IP 核設(shè)計 PCIe 協(xié)議 RAID0


【摘要】:隨著信息社會的發(fā)展,數(shù)據(jù)量呈爆炸式增長,因而對存儲系統(tǒng)性能提出了更高的要求。傳統(tǒng)固態(tài)硬盤(SSD)采用的SATA、SAS等接口已經(jīng)逐漸落后于高速增長的硬盤帶寬,成為高帶寬、大容量數(shù)據(jù)存儲系統(tǒng)發(fā)展的瓶頸;赑CIe接口的SSD以其高性能和低功耗的特性得到了更多的青睞。本文完成了基于FPGA的大容量存儲模塊硬件電路的設(shè)計,同時探討了如何利用FPGA豐富的邏輯資源來實現(xiàn)NVMe協(xié)議,并且將數(shù)據(jù)以RAID 0方式實時寫入SSD陣列,使CPU能通過PCIe接口訪問固態(tài)存儲系統(tǒng)。在FPGA邏輯設(shè)計過程中,本文根據(jù)NVMe協(xié)議的特征和實現(xiàn)過程設(shè)計了基于全交換互連結(jié)構(gòu)IP核的FPGA工程架構(gòu),研究了基于AXI4總線協(xié)議的自定義IP核,實現(xiàn)對PCIe總線數(shù)據(jù)的接收、解析、緩存、發(fā)送等功能。經(jīng)實驗驗證,利用FPGA基于NVMe協(xié)議來實現(xiàn)RAID0存儲構(gòu)架,方案明確、設(shè)計合理,能滿足較高的系統(tǒng)數(shù)據(jù)吞吐與處理要求。實際寫速率達到5.12GB/S,讀速率達到5.4GB/s。RAID 0的并行處理機制可以使多個獨立的PCIe SSD協(xié)調(diào)工作,相較于CPU直接訪問單塊硬盤,有效增加了存儲系統(tǒng)的帶寬和容量。
[Abstract]:With the development of the information society, the amount of data increases explosively, so the performance of the storage system is required higher. The traditional solid-state hard disk (SSD) uses SATA. SAS and other interfaces have gradually lagged behind the high-speed growth of hard disk bandwidth, becoming a high bandwidth. The bottleneck of the development of large capacity data storage system. SSD based on PCIe interface is more popular for its high performance and low power consumption. In this paper, the hardware of large capacity storage module based on FPGA is completed. Road design. At the same time, it discusses how to use the rich logic resources of FPGA to realize the NVMe protocol, and write the data into SSD array in RAID 0 mode in real time. CPU can access solid state storage system through PCIe interface. In the process of FPGA logic design. According to the characteristics and implementation process of NVMe protocol, this paper designs the FPGA engineering architecture based on the IP core of all-switched interconnection structure, and studies the self-defined IP core based on AXI4 bus protocol. PCIe bus data to achieve the reception, analysis, cache, sending and other functions. After experimental verification, the use of FPGA based on NVMe protocol to achieve RAID0 storage framework, the scheme is clear, reasonable design. It can meet the requirements of high throughput and processing of system data. The actual write rate is 5.12GB / S. The parallel processing mechanism with read rate of 5.4 GB / s. Raid 0 enables multiple independent PCIe SSD to work together, compared with CPU to directly access a single hard disk. It effectively increases the bandwidth and capacity of the storage system.
【學(xué)位授予單位】:浙江大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2017
【分類號】:TP333

【參考文獻】

相關(guān)期刊論文 前10條

1 張曉雄;;電源分配網(wǎng)絡(luò)的直流壓降分析與研究[J];電子技術(shù)與軟件工程;2016年18期

2 張s,

本文編號:1381219


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