本文關鍵詞：一種高速加法器—前置進位加法器研究與設計　出處：《西南交通大學》2015年碩士論文　論文類型：學位論文

  更多相關文章： 前置進位 多米諾邏輯 自定時時鐘 點操作 進位樹 高速加法器

【摘要】：加法器是最基本最常用的算術運算單元,它通常也是限制芯片工作速度的主要因素,高速加法器的設計是必需的。本文采用全定制的方法,進行單元模塊電路層次的設計,以及算法層次的優(yōu)化,以此來提高加法器的速度。雖然全定制設計時間周期較長,但是它設計靈活,能顯著提高加法器性能。本文先從加法器的整體算法著手,比較了傳統(tǒng)的行波進位算法,和采用進位樹的前置進位算法。然后引進前置進位信號(包括進位產(chǎn)生信號,進位消除信號,進位傳播信號),并根據(jù)點操作原理,采用三種前置進位樹(分別是Kogge-Stone樹、Han-Carlson樹和Brent-Kung樹)設計加法器,并對電路速度和面積進行優(yōu)化。最后對優(yōu)化后的延遲時間、晶體管數(shù)量進行比較,比較結果表明32位Kogge-Stone樹形結構的加法器延時最小,晶體管數(shù)量最多,32位Brent-Kung樹形結構的加法器延時最大,晶體管數(shù)量最少,32位Han-Carlson樹形結構的加法器延時和晶體管數(shù)量在三種進位樹中都居中。本文先進行單元模塊電路設計,然后搭建三種前置進位樹,最后搭建三種樹形結構前置進位加法器。單元電路的設計,即進位信號產(chǎn)生電路,進位樹單元電路,和求和單元電路,都采用含有靜態(tài)泄露器的動態(tài)電路。在進位樹的搭建過程中,使用多米諾邏輯和自定時時鐘相結合的方法來減小競爭與冒險,增加時鐘的利用率并實現(xiàn)電路功能。在Cadence平臺下,用XB0.35um工藝,設計32位高速前置進位加法器。運用仿真工具Spectre對電路仿真并進行功能驗證,結果顯示32位Han-Carlson樹形前置進位加法器,32位Brent-Kung樹形前置進位加法器,32位Kogge-Stone樹形前置進位加法器優(yōu)化后的最大延時為6.15ns,6.47ns和5.76ns,分別比最大延時為52.5ns的傳統(tǒng)行波進位加法器快了7.54,7.11和8.11倍,完成了高速加法器的設計任務。
[Abstract]:Adder is the most basic and most commonly used arithmetic unit. It is also the main factor that limits the speed of the chip. The design of high-speed adder is necessary. The method of full customization is adopted in this paper. In order to improve the speed of adder, the circuit level of unit module and the optimization of algorithm level are carried out. Although the design time period is long, the design is flexible. It can improve the performance of adder significantly. Firstly, this paper compares the traditional traveling wave carry algorithm with the whole algorithm of adder. And the carry tree precarry algorithm is used. Then the leading carry signal (including carry generation signal, carry cancellation signal, carry propagation signal) is introduced, and according to the principle of point operation. Three kinds of precarried trees (Kogge-Stone tree Han-Carlson tree and Brent-Kung tree) are used to design the adder. The circuit speed and area are optimized. Finally, the delay time and the number of transistors after optimization are compared. The comparison results show that the adder with 32-bit Kogge-Stone tree structure has the minimum delay time. The maximum number of transistors is 32 bit Brent-Kung tree structure with the largest delay and the least number of transistors. The delay of adder and the number of transistors in 32-bit Han-Carlson tree are all centered in the three carry trees. In this paper, the circuit of cell module is designed first, and then three kinds of pre-carry trees are built. Finally, three kinds of tree structure carry adder are built. The design of cell circuit, namely carry signal generation circuit, carry tree unit circuit, and summation unit circuit. In the process of building carry tree, domino logic and self-timing clock are combined to reduce competition and risk. Increase the utilization rate of clock and realize the circuit function. Under the Cadence platform, use XB0.35um technology. The 32-bit high speed carry adder is designed. The circuit is simulated and verified by Spectre. The result shows that the 32-bit Han-Carlson tree is the leading carry adder. The maximum delay of 32-bit Brent-Kung tree forecarry adder is 6.15ns after the optimization of 32-bit Kogge-Stone tree carry adder. 6.47ns and 5.76ns are 7.54 and 8.11 times faster than the traditional traveling wave carry adder with the maximum delay of 52.5ns, respectively. The design task of the high-speed adder is completed.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP342.2

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1 劉泰興;一種高速加法器—前置進位加法器研究與設計[D];西南交通大學;2015年

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本文編號：1381137