本文關(guān)鍵詞：一種高速加法器—前置進(jìn)位加法器研究與設(shè)計(jì)　出處：《西南交通大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 前置進(jìn)位 多米諾邏輯 自定時(shí)時(shí)鐘 點(diǎn)操作 進(jìn)位樹 高速加法器

【摘要】：加法器是最基本最常用的算術(shù)運(yùn)算單元,它通常也是限制芯片工作速度的主要因素,高速加法器的設(shè)計(jì)是必需的。本文采用全定制的方法,進(jìn)行單元模塊電路層次的設(shè)計(jì),以及算法層次的優(yōu)化,以此來提高加法器的速度。雖然全定制設(shè)計(jì)時(shí)間周期較長,但是它設(shè)計(jì)靈活,能顯著提高加法器性能。本文先從加法器的整體算法著手,比較了傳統(tǒng)的行波進(jìn)位算法,和采用進(jìn)位樹的前置進(jìn)位算法。然后引進(jìn)前置進(jìn)位信號(包括進(jìn)位產(chǎn)生信號,進(jìn)位消除信號,進(jìn)位傳播信號),并根據(jù)點(diǎn)操作原理,采用三種前置進(jìn)位樹(分別是Kogge-Stone樹、Han-Carlson樹和Brent-Kung樹)設(shè)計(jì)加法器,并對電路速度和面積進(jìn)行優(yōu)化。最后對優(yōu)化后的延遲時(shí)間、晶體管數(shù)量進(jìn)行比較,比較結(jié)果表明32位Kogge-Stone樹形結(jié)構(gòu)的加法器延時(shí)最小,晶體管數(shù)量最多,32位Brent-Kung樹形結(jié)構(gòu)的加法器延時(shí)最大,晶體管數(shù)量最少,32位Han-Carlson樹形結(jié)構(gòu)的加法器延時(shí)和晶體管數(shù)量在三種進(jìn)位樹中都居中。本文先進(jìn)行單元模塊電路設(shè)計(jì),然后搭建三種前置進(jìn)位樹,最后搭建三種樹形結(jié)構(gòu)前置進(jìn)位加法器。單元電路的設(shè)計(jì),即進(jìn)位信號產(chǎn)生電路,進(jìn)位樹單元電路,和求和單元電路,都采用含有靜態(tài)泄露器的動態(tài)電路。在進(jìn)位樹的搭建過程中,使用多米諾邏輯和自定時(shí)時(shí)鐘相結(jié)合的方法來減小競爭與冒險(xiǎn),增加時(shí)鐘的利用率并實(shí)現(xiàn)電路功能。在Cadence平臺下,用XB0.35um工藝,設(shè)計(jì)32位高速前置進(jìn)位加法器。運(yùn)用仿真工具Spectre對電路仿真并進(jìn)行功能驗(yàn)證,結(jié)果顯示32位Han-Carlson樹形前置進(jìn)位加法器,32位Brent-Kung樹形前置進(jìn)位加法器,32位Kogge-Stone樹形前置進(jìn)位加法器優(yōu)化后的最大延時(shí)為6.15ns,6.47ns和5.76ns,分別比最大延時(shí)為52.5ns的傳統(tǒng)行波進(jìn)位加法器快了7.54,7.11和8.11倍,完成了高速加法器的設(shè)計(jì)任務(wù)。
[Abstract]:Adder is the most basic and most commonly used arithmetic unit. It is also the main factor that limits the speed of the chip. The design of high-speed adder is necessary. The method of full customization is adopted in this paper. In order to improve the speed of adder, the circuit level of unit module and the optimization of algorithm level are carried out. Although the design time period is long, the design is flexible. It can improve the performance of adder significantly. Firstly, this paper compares the traditional traveling wave carry algorithm with the whole algorithm of adder. And the carry tree precarry algorithm is used. Then the leading carry signal (including carry generation signal, carry cancellation signal, carry propagation signal) is introduced, and according to the principle of point operation. Three kinds of precarried trees (Kogge-Stone tree Han-Carlson tree and Brent-Kung tree) are used to design the adder. The circuit speed and area are optimized. Finally, the delay time and the number of transistors after optimization are compared. The comparison results show that the adder with 32-bit Kogge-Stone tree structure has the minimum delay time. The maximum number of transistors is 32 bit Brent-Kung tree structure with the largest delay and the least number of transistors. The delay of adder and the number of transistors in 32-bit Han-Carlson tree are all centered in the three carry trees. In this paper, the circuit of cell module is designed first, and then three kinds of pre-carry trees are built. Finally, three kinds of tree structure carry adder are built. The design of cell circuit, namely carry signal generation circuit, carry tree unit circuit, and summation unit circuit. In the process of building carry tree, domino logic and self-timing clock are combined to reduce competition and risk. Increase the utilization rate of clock and realize the circuit function. Under the Cadence platform, use XB0.35um technology. The 32-bit high speed carry adder is designed. The circuit is simulated and verified by Spectre. The result shows that the 32-bit Han-Carlson tree is the leading carry adder. The maximum delay of 32-bit Brent-Kung tree forecarry adder is 6.15ns after the optimization of 32-bit Kogge-Stone tree carry adder. 6.47ns and 5.76ns are 7.54 and 8.11 times faster than the traditional traveling wave carry adder with the maximum delay of 52.5ns, respectively. The design task of the high-speed adder is completed.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TP342.2

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1 劉泰興;一種高速加法器—前置進(jìn)位加法器研究與設(shè)計(jì)[D];西南交通大學(xué);2015年

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本文編號：1381137